发明授权
- 专利标题: Multiple level storage DRAM cell
- 专利标题(中): 多级存储DRAM单元
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申请号: US779994申请日: 1996-12-23
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公开(公告)号: US5771187A公开(公告)日: 1998-06-23
- 发明人: Ashok Kapoor
- 申请人: Ashok Kapoor
- 申请人地址: CA Milpitas
- 专利权人: LSI Logic Corporation
- 当前专利权人: LSI Logic Corporation
- 当前专利权人地址: CA Milpitas
- 主分类号: G11C11/56
- IPC分类号: G11C11/56 ; G11C11/24
摘要:
A semiconductor memory device which includes a word line, a bit line and a storage capacitor having first and second ends. A pair of FEATS each having gates coupled to the word line and one side coupled to the bit line. The other side of each FEAT is coupled to a storage capacitor upon which a selected one of four potential levels, corresponding to stored values of zero, one, two, or three, can be stored and thereafter read. One of the FEATS has a thicker gate oxide than the other and thus a higher threshold voltage. Voltage stored on the capacitor is read in two cycles thereby producing in the first cycle a high level pulse, a low level pulse, or no pulse and in the second cycle, a low level pulse or no pulse, depending upon the level of charge stored on the capacitor.
公开/授权文献
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