发明授权
US5786616A Semiconductor integrated circuit having an SOI structure, provided with
a protective circuit
失效
具有SOI结构的半导体集成电路，具有保护电路
- 专利标题： Semiconductor integrated circuit having an SOI structure, provided with a protective circuit
- 专利标题（中）： 具有SOI结构的半导体集成电路，具有保护电路
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申请号： US926997申请日： 1997-09-10
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公开(公告)号： US5786616A公开(公告)日： 1998-07-28
- 发明人: Harutsugu Fukumoto , Hiroaki Tanaka , Akiyoshi Asai
- 申请人： Harutsugu Fukumoto , Hiroaki Tanaka , Akiyoshi Asai
- 申请人地址： JPX Kariya
- 专利权人： Nippondenso, Co., Ltd.
- 当前专利权人： Nippondenso, Co., Ltd.
- 当前专利权人地址： JPX Kariya
- 优先权： JPX6-222902 19940919
- 主分类号： H01L27/04
- IPC分类号： H01L27/04 ; H01L21/822 ; H01L21/8238 ; H01L27/02 ; H01L27/08 ; H01L27/092 ; H01L27/12 ; H01L29/786
摘要：
A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed. An electrostatic withstand quantity of the inverter circuit can be increased.
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