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1.发明授权Semiconductor integrated circuit having an SOI structure, provided with a protective circuit 失效具有SOI结构的半导体集成电路，具有保护电路
公开(公告)号：US5786616A
公开(公告)日：1998-07-28
申请号：US926997
申请日：1997-09-10
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786
CPC分类号： H01L27/0251 , H01L27/1203
摘要： A SOI semiconductor integrate circuit device, which can protect against surges between a signal-input terminal and power-supply input terminal thereof to obtain an improved electrostatic withstand quantity, is disclosed. An inverter circuit which is an integrated circuit is formed in a thin-film semiconductor layer formed through an insulation film on a p-type silicon substrate. An n-type diode diffusion region, resistor diffusion region, and FET diffusion region are formed within the silicon substrate. An input portion of the inverter circuit is connected through the resistor diffusion region to a signal-input terminal IN. A power-supply input terminal VC is connected to a ground terminal GND through a reverse-biased diode D formed by the diode diffusion region. When surge is applied to the signal-input terminal IN, a parasitic diode DD composed by the resistor diffusion region and silicon substrate exhibits avalanche breakdown and surge voltage is bypassed. An electrostatic withstand quantity of the inverter circuit can be increased.
摘要翻译： 公开了一种SOI半导体集成电路器件，其可以防止信号输入端子和其电源输入端子之间的浪涌以获得改善的静电耐受量。 作为集成电路的逆变器电路形成在通过p型硅衬底上的绝缘膜形成的薄膜半导体层中。 在硅衬底内形成n型二极管扩散区，电阻扩散区和FET扩散区。 反相器电路的输入部分通过电阻器扩散区域连接到信号输入端子IN。 电源输入端子VC通过由二极管扩散区形成的反向偏置二极管D连接到接地端子GND。 当浪涌被施加到信号输入端子IN时，由电阻器扩散区域和硅衬底组成的寄生二极管DD表现为雪崩击穿，旁路浪涌电压。 可以增加逆变器电路的静电耐受量。
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公开(公告)号：US5914515A
公开(公告)日：1999-06-22
申请号：US499472
申请日：1995-07-07
IPC分类号： H01L29/78 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/1203
摘要： A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs. A bias voltage switching circuit applies electric potentials to the bias electrodes for the P-channel and the N-channel to increase the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in a waiting state and applies the electric potentials to the bias electrodes for the P-channel and the N-channel to reduce the respective absolute values of threshold voltages of the P-channel type and N-channel type MOSFETs when the MOSFETs are in an operating state.
摘要翻译： 公开了一种半导体器件，其可以在需要这种操作时实现具有小的漏电流的晶体管的高速操作。 通过氧化硅膜在单晶硅基板上形成SOI层，在层上配置有P沟道型MOSFET和N沟道型MOSFET的C-MOS电路（反相电路）。 用于P沟道的偏置电极设置在面向P沟道型MOSFET的氧化硅膜内，而用于N沟道的偏置电极设置在面对N沟道型MOSFET的氧化硅膜内。 偏置电压切换电路为P沟道和N沟道的偏置电极施加电位，以在MOSFET等待时增加P沟道型和N沟道型MOSFET的阈值电压的绝对值 并且当MOSFET处于工作状态时，将电位施加到P沟道和N沟道的偏置电极以减小P沟道型和N沟道型MOSFET的阈值电压的相应绝对值。
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公开(公告)号：US06272513B1
公开(公告)日：2001-08-07
申请号：US09253741
申请日：1999-02-22
IPC分类号： G06F752
CPC分类号： G06F7/5338 , G06F7/49994
摘要： A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the multiplier data has n bits, where n denotes a predetermined even number. A 1-bit sign extension of the multiplicand data is executed to generate data having n+1 bits. In the multiplying device, n/2 partial product data pieces are generated on the basis of the data having n+1 bits and the multiplier data according to second-order Booth's algorithm. Each of the n/2 partial product data pieces has n+1 bits. There is a plurality of adders connected and arranged in a tree configuration. The adders operate for adding the n/2 partial product data pieces. The adders include a final-stage adder which outputs multiplication result data representing a product of the multiplicand data and the multiplier data. The multiplication result data has 2n−1 bits. In the tree arrangement of the adders, there is provided a plurality of sign extension elements for implementing sign extensions of one data pieces, which correspond to lower bits of the multiplier data, in pairs of data pieces inputted into the adders.
摘要翻译： 乘法装置用于以二进制补码表示形式实现乘法数据与乘法器数据之间的乘法。 被乘数数据和乘法器数据中的每一个具有n位，其中n表示预定偶数。 执行被乘数数据的1位符号扩展，以生成具有n + 1位的数据。 在乘法装置中，根据具有n + 1比特的数据和根据二阶布斯算法的乘数数据生成n / 2个部分乘积数据。 n / 2个部分乘积数据中的每一个具有n + 1位。 存在以树形结构连接和布置的多个加法器。 加法器用于添加n / 2个部分产品数据。 加法器包括最终级加法器，其输出表示乘法器数据和乘法器数据的乘积的乘法结果数据。 乘法结果数据具有2n-1位。 在加法器的树形结构中，提供了多个符号扩展元件，用于实现输入到加法器中的成对数据片段对应于乘法器数据的较低位的一个数据段的符号扩展。
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4.发明授权Information processing apparatus having a CPU and an auxiliary arithmetic unit for achieving high-speed operation 有权具有用于实现高速操作的CPU和辅助运算单元的信息处理设备公开(公告)号：US06249858B1
公开(公告)日：2001-06-19
申请号：US09250134
申请日：1999-02-16
IPC分类号： G06F9302
CPC分类号： G06F9/3879
摘要： An information processing apparatus such as a microcomputer consisting of a CPU and a coprocessor is provided. The CPU and the coprocessor are connected through a data bus and an address bus. Switches are disposed in the data bus and the address bus which block communication between the CPU and the coprocessor upon execution of an instruction in the coprocessor, thereby allowing the CPU 1 to operate in parallel to the coprocessor.
摘要翻译： 提供了诸如由CPU和协处理器组成的微型计算机的信息处理装置。 CPU和协处理器通过数据总线和地址总线连接。 开关设置在数据总线和地址总线中，该地址总线在执行协处理器中的指令时阻止CPU与协处理器之间的通信，从而允许CPU 1与协处理器并行操作。
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5.发明授权
公开(公告)号：US6003127A
公开(公告)日：1999-12-14
申请号：US725709
申请日：1996-10-04
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/30167
摘要： A pipeline processing apparatus for performing processing operations in a succession of processing cycles, in which each cycle is composed of a succession of stages that include an instruction decoding stage for decoding an instruction associated with the cycle and an execution stage for executing an operation dependent on the instruction, and the processing cycles include a first cycle which starts at a first time and a second cycle that begins at a second time that is after the first time and that overlaps the first cycle in time. The apparatus is constructed and controlled for causing a branch instruction to be decoded in the instruction decoding stage of the first cycle; and for effecting a calculation in the execution stage of the first cycle, dependent on the branch instruction decoded in the instruction decoding stage of the first cycle.
摘要翻译： 一种流水线处理装置，用于在一系列处理周期中执行处理操作，其中每个周期由包括用于解码与该周期相关联的指令的指令解码级的一系列级组成，以及用于执行依赖于 指令和处理周期包括从第一时间开始的第一周期和从第一次开始的第二个周期开始并且与第一周期重叠的第二周期。 该装置被构造和控制，用于使分支指令在第一周期的指令解码阶段被解码; 并且用于在第一周期的执行阶段中进行计算，这取决于在第一周期的指令解码阶段中解码的分支指令。
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6.发明授权公开(公告)号：US06308263B1
公开(公告)日：2001-10-23
申请号：US09429022
申请日：1999-10-29
IPC分类号： G06F942
CPC分类号： G06F9/3804 , G06F9/30058 , G06F9/30167
摘要： A decoder decodes a branch instruction. An operating section executes logical, arithmetic, and shift operations. A register file store operation result of the operating section. A program counter counting the address of the present programs. A direct-setting bus is provided to allowing the decoder to directly set an immediate value to the program counter without passing through an output bus of the operating section. And, a switch selectively connects the direct-setting bus or the output bus to the program counter.
摘要翻译： 解码器解码分支指令。 操作部分执行逻辑，算术和移位操作。 操作部分的注册文件存储操作结果。 一个程序计数器，用于计数当前程序的地址。 提供直接设置总线以允许解码器直接将程序计数器设置为不经过操作部分的输出总线的程序计数器。 而且，开关选择性地将直接设置总线或输出总线连接到程序计数器。
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公开(公告)号：US5729725A
公开(公告)日：1998-03-17
申请号：US733734
申请日：1996-10-17
申请人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
CPC分类号： G06F7/764
摘要： With N-bit mask bit data, a bit mask generator generates (L.times.M.times.N)-bit mask data in which the N-bit mask bit data is disposed in one of L.times.M consistent blocks which is specified by M-bit block selection data and L-bit super-block selection data and each bit of the other blocks are stuffed with a stuffing bit. The bit mask generator comprises a first mask generator responsive to the block selection data for generating first mask data by disposing the N-bit mask bit data in one of M blocks of N bits which is specified by one of the M-bit block selection data, and a second mask generator responsive to the super-block selection data for generating the final mask data by disposing the first mask data in one of L super-blocks of M blocks which is specified by one of the L-bit super-block selection data. A bit field operation is performed by using the generated mask data.
摘要翻译： 利用N位屏蔽位数据，位掩码生成器产生（LxM×N）位掩码数据，其中N位掩码位数据被布置在由M位块选择数据和L位M位块选择数据指定的LxM一致块之一中， 位超块选择数据，并且其他块的每个位都填充有填充位。 位掩码生成器包括响应于块选择数据的第一掩码生成器，用于通过将N位掩码位数据设置在由M位块选择数据之一指定的N位的M个块之一中来产生第一掩码数据 以及第二掩模生成器，其响应于超块选择数据，用于通过将第一掩模数据设置在由L位超块选择之一指定的M个块的L个超块中的一个中来产生最终掩模数据 数据。 通过使用所生成的掩码数据来执行位场操作。
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8.发明授权Method and apparatus for performing exception processing routine in pipeline processing 失效在流水线处理中执行异常处理程序的方法和装置
公开(公告)号：US5938762A
公开(公告)日：1999-08-17
申请号：US726753
申请日：1996-10-07
CPC分类号： G06F9/322 , G06F9/3861
摘要： An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine. Thereafter, the normal processing sequence control is stopped, and the exception processing routine is performed in the exception processing sequence control.
摘要翻译： 一种信息处理装置和方法，当在微处理器中发生中断时，开始异常处理顺序控制，中断程序的程序条件和中断程序的地址被保存在RAM中，程序地址 从异常处理生成源读出跳转指令，并将其设置在程序计数器中，并停止异常处理顺序控制。 此后，开始通常的处理顺序控制，从ROM读出跳转指令，根据跳转指令计算出异常处理向量的地址，从ROM中读出异常处理向量，分支地址 在程序计数器中设置由异常处理向量指示的异常处理程序，并且将微处理器的操作状态分支到异常处理程序。 此后，停止正常处理顺序控制，并且在异常处理顺序控制中执行异常处理程序。
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公开(公告)号：US5877973A
公开(公告)日：1999-03-02
申请号：US806213
申请日：1997-02-26
申请人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
发明人： Koji Kato , Harutsugu Fukumoto , Hiroaki Tanaka
摘要： An 8-bit CLA adder is constructed for inputting 4 lower bits a3:0,b3:0 and 4 upper bits a7:4,b7:4 of two input signals to the two 4-bit full adders 2,12 and a carry c-1 to the lowest bit the full adder of the first-stage 2 to generate carries c3,c7 correspondint to the third and seventh bit of the input signals from a carry generation signal g7:0 and a carry propagation signal p7:0 generated by the both adders 2,12 and the carry c-1. The full adder of the second-stage 12 is constructed to add the 4 upper bits a7:4,b7:4 with setting a carry-in as 0 so as to generate a temporary summing signal sz7:4. A logical circuit 14 generates a true sum of 4 upper bits from a carry c3 to the third bit to the forth bit, a temporary sum sz7:4 and a carry propagation signal p7:4 generated by the full adder of the second-stage 12.
摘要翻译： 一个8位CLA加法器被构造用于将两个输入信号的4个低位位a3：0，b3：0和4个高位位a7：4，b7：4输入到两个4位全加器2,12和一个进位c -1到第一级2的全加器的最低位，以产生载波c3，c7，对应于来自进位产生信号g7：0的输入信号的第三和第七位以及由...生成的进位传播信号p7：0 两个加法器2,12和进位c-1。 第二级12的全加器被构造为通过将进位设置为0来添加4个高位位a7：4，b7：4，以产生临时求和信号sz7：4。 逻辑电路14产生从进位c3到第三位到第四位的4个高位的真和，由第二级12的全加器产生的临时和sz7：4和进位传播信号p7：4 。
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10.发明授权Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit 失效具有时钟控制功能的管道算术和逻辑系统，用于选择性地为给定单元提供时钟
公开(公告)号：US5771376A
公开(公告)日：1998-06-23
申请号：US725495
申请日：1996-10-04
CPC分类号： G06F9/30043 , G06F9/325 , G06F9/3867 , G06F9/3869
摘要： A pipeline arithmetic and logic system capable of adjusting operational timings among stages without using an NOP instruction, providing a size reduction of its control section. The system has a decoder set including decoder groups divided into a decoder group for controlling an arithmetic section unit, a register file unit and a program counter unit, and a decoder for control of an address unit, and further including a clock control unit controlled by the address unit control decoder. A clock signal from an external source is directly fed to the address unit while being fed through the clock control unit to the other units. When fetching a data transfer instruction and repeatedly executing an MA stage twice, the system stops the clock control unit at the execution of the first MA stage to inhibit the operations of the units other than the address unit.
摘要翻译： 一种管道算术和逻辑系统，其能够在不使用NOP指令的情况下调整阶段之间的操作定时，从而提供其控制部分的尺寸减小。 该系统具有解码器组，其包括被分成用于控制算术部分单元的解码器组，寄存器文件单元和程序计数器单元的解码器组，以及用于控制地址单元的解码器，还包括由 地址单元控制解码器。 来自外部源的时钟信号直接馈送到地址单元，同时通过时钟控制单元馈送到其它单元。 当获取数据传输指令并重复执行MA阶段两次时，系统在执行第一MA级停止时钟控制单元以禁止地址单元以外的单元的操作。
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