- 专利标题： Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices
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申请号： US555283申请日： 1995-11-08
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公开(公告)号： US5802540A公开(公告)日： 1998-09-01
- 发明人: Chiakang Sung , Joseph Huang , Wanli Chang
- 申请人： Chiakang Sung , Joseph Huang , Wanli Chang
- 申请人地址： CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： CA San Jose
- 主分类号： G11C8/04
- IPC分类号： G11C8/04 ; G11C8/12 ; H03K19/177 ; G06F12/02
摘要：
A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.
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