发明授权
US5804479A Method for forming semiconductor integrated circuit device having a
capacitor
失效
用于形成具有电容器的半导体集成电路器件的方法
- 专利标题: Method for forming semiconductor integrated circuit device having a capacitor
- 专利标题(中): 用于形成具有电容器的半导体集成电路器件的方法
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申请号: US694665申请日: 1996-08-09
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公开(公告)号: US5804479A公开(公告)日: 1998-09-08
- 发明人: Hideo Aoki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita , Takashi Hayakawa , Katsutoshi Matsunaga , Kazuhiko Saitoh , Michio Nishimura , Minoru Ohtsuka , Katsuo Yuhara , Michio Tanaka , Yuji Ezaki , Toshiyuki Kaeriyama , SongSu Cho
- 申请人: Hideo Aoki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Keizo Kawakita , Takashi Hayakawa , Katsutoshi Matsunaga , Kazuhiko Saitoh , Michio Nishimura , Minoru Ohtsuka , Katsuo Yuhara , Michio Tanaka , Yuji Ezaki , Toshiyuki Kaeriyama , SongSu Cho
- 申请人地址: JPX Tokyo TX Dallas
- 专利权人: Hitachi, Ltd.,Texas Instruments Inc.
- 当前专利权人: Hitachi, Ltd.,Texas Instruments Inc.
- 当前专利权人地址: JPX Tokyo TX Dallas
- 优先权: JPX7-203064 19950809; JPX8-154589 19960614
- 主分类号: H01L21/302
- IPC分类号: H01L21/302 ; H01L21/3065 ; H01L21/822 ; H01L21/8239 ; H01L21/8242 ; H01L27/04 ; H01L27/105 ; H01L27/108
摘要:
The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.
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