发明授权
US5812334A Synchronous read channel employing discrete timing recovery, transition
detector, and sequence detector
失效
采用离散定时恢复,转换检测器和序列检测器的同步读取通道
- 专利标题: Synchronous read channel employing discrete timing recovery, transition detector, and sequence detector
- 专利标题(中): 采用离散定时恢复,转换检测器和序列检测器的同步读取通道
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申请号: US210302申请日: 1994-03-16
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公开(公告)号: US5812334A公开(公告)日: 1998-09-22
- 发明人: Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
- 申请人: Richard T. Behrens , Kent D. Anderson , Alan Armstrong , Trent Dudley , Bill Foland , Neal Glover , Larry King
- 申请人地址: CA Fremont
- 专利权人: Cirrus Logic, Inc.
- 当前专利权人: Cirrus Logic, Inc.
- 当前专利权人地址: CA Fremont
- 主分类号: G11B5/012
- IPC分类号: G11B5/012 ; G11B5/09 ; G11B20/10 ; G11B20/12 ; G11B20/14 ; G11B20/18 ; G11B27/30 ; H03M13/31
摘要:
A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.
公开/授权文献
- USD312160S Trash can 公开/授权日:1990-11-13
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