公开(公告)号：US5812334A

公开(公告)日：1998-09-22

申请号：US210302

申请日：1994-03-16

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

公开(公告)号：US5424881A

公开(公告)日：1995-06-13

申请号：US12266

申请日：1993-02-01

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan Armstrong ,  Trent Dudley ,  Bill Foland ,  Neal Glover ,  Larry King

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31 ,  G06F11/10 ,  G11B20/16

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

公开(公告)号：US09407875B2

公开(公告)日：2016-08-02

申请号：US13303926

申请日：2011-11-23

申请人： Alan Armstrong

发明人： Alan Armstrong

IPC分类号： H04N9/80 ,  H04N7/167 ,  H04N21/436 ,  H04N21/4367 ,  H04N21/4405 ,  H04N21/4623 ,  H04L29/06

CPC分类号： H04N21/4408 ,  H04L63/0428 ,  H04N7/1675 ,  H04N21/43622 ,  H04N21/4367 ,  H04N21/4385 ,  H04N21/4405 ,  H04N21/4623 ,  H04N21/64322

摘要： An apparatus includes an input circuit, a storage device, a retrieve circuit, a decrypt circuit, and an output circuit. The input circuit is configured to receive packets of encrypted encoded video data from a first network. The storage device is preauthorized by the first network to store the encrypted encoded video data. The retrieve circuit is configured to retrieve the encrypted encoded video data from the storage device for decryption. The decrypt circuit is configured to decrypt the encrypted encoded video data without further authorization. The output circuit is configured to transmit a signal representing the encrypted encoded video data while the retrieve circuit retrieves the encrypted encoded video data from the storage device.

摘要翻译： 一种装置包括输入电路，存储装置，检索电路，解密电路和输出电路。 输入电路被配置为从第一网络接收加密的编码视频数据的分组。 存储设备由第一网络预先授权以存储加密的编码视频数据。 检索电路被配置为从存储装置检索加密的编码视频数据以进行解密。 解密电路被配置为在没有进一步授权的情况下解密加密的编码视频数据。 输出电路被配置为当检索电路从存储设备检索加密的编码视频数据时，发送表示加密的编码视频数据的信号。

公开(公告)号：US08161215B2

公开(公告)日：2012-04-17

申请号：US13245269

申请日：2011-09-26

申请人： Alan Armstrong

发明人： Alan Armstrong

IPC分类号： G06F13/12 ,  G06F13/38

CPC分类号： G06F3/0674 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0676 ,  G06F12/00

摘要： A system including a network interface module, a first processor, a hard disk control module, and a second processor. The network interface module is configured to communicate with a network. The first processor is configured to communicate with the network interface module and perform processing related to communication of a hard disk drive with the network via the network interface module. The hard disk control module is configured to communicate with the first processor and control operation of the hard disk drive. The second processor is configured to communicate with the hard disk control module and perform processing related to storing data on the hard disk drive. The second processor and the hard disk control module are configured to process packets communicated via the network interface module using a hyper-text transfer protocol, a peer-to-peer sharing protocol, and an Internet protocol-based small computer system interface standard.

摘要翻译： 一种包括网络接口模块，第一处理器，硬盘控制模块和第二处理器的系统。 网络接口模块被配置为与网络通信。 第一处理器被配置为与网络接口模块进行通信，并通过网络接口模块执行与网络通信的硬盘驱动器的处理。 硬盘控制模块被配置为与第一处理器通信并控制硬盘驱动器的操作。 第二处理器被配置为与硬盘控制模块进行通信，并执行与在硬盘驱动器上存储数据有关的处理。 第二处理器和硬盘控制模块被配置为使用超文本传输​​协议，对等共享协议和基于因特网协议的小型计算机系统接口标准来处理经由网络接口​​模块传送的分组。

公开(公告)号：US20080140921A1

公开(公告)日：2008-06-12

申请号：US12032221

申请日：2008-02-15

申请人： Sehat Sutardja ,  Alan Armstrong

发明人： Sehat Sutardja ,  Alan Armstrong

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F3/0656 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/313 ,  Y02D10/13 ,  Y02D10/154

摘要： A hard disk drive system comprises a hard disk assembly (HDA) comprises a magnetic medium that stores data. A spindle motor rotates the magnetic medium. A read/write element writes the data to and reads the data from the magnetic medium. A first connector arranged on the HDA receives a removable non-volatile semiconductor memory module. Portions of the data of the magnetic medium are selectively cached in the removable non-volatile semiconductor memory module. A hard disk control (HDC) module controls the HDA. A flex cable provides a connection between the HDC module and the spindle motor, the first connector, the removable non-volatile semiconductor memory module and the read/write element.

摘要翻译： 硬盘驱动器系统包括硬盘组件（HDA），其包括存储数据的磁介质。 主轴电机旋转磁性介质。 读/写元件将数据写入磁介质并从其读取数据。 布置在HDA上的第一连接器接收可拆卸的非易失性半导体存储器模块。 磁性介质的数据的一部分被选择性地高速缓存在可移除的非易失性半导体存储器模块中。 硬盘控制（HDC）模块控制HDA。 柔性电缆提供HDC模块和主轴电机，第一连接器，可移动非易失性半导体存储器模块和读/写元件之间的连接。

公开(公告)号：US07308530B1

公开(公告)日：2007-12-11

申请号：US10679030

申请日：2003-10-02

申请人： Alan Armstrong ,  Justin Heindel ,  Sehat Sutardja ,  Saeed Azimi ,  Joseph Sheredy

发明人： Alan Armstrong ,  Justin Heindel ,  Sehat Sutardja ,  Saeed Azimi ,  Joseph Sheredy

IPC分类号： G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/0611 ,  G06F3/0676

摘要： A data storage device architecture includes a HDA printed circuit board (PCB) including a spindle motor driver, a read/write arm driver, a read channel driver, and a first input/output (I/O) interface that are arranged on the HDA PCB. An application PCB includes at least one of an application specific integrated circuit and a processor that performs application and hard drive control related processing. A buffer stores application and hard drive control related data. A hard drive controller (HDC), a mapping driver, and a second I/O interface are arranged on the application PCB. The second I/O interface communicates with the first I/O interface. The mapping driver is capable of at least one of mapping logical addresses to physical addresses and monitoring a location of a read/write head.

摘要翻译： 数据存储设备架构包括HDA印刷电路板（PCB），其包括主轴电机驱动器，读/写臂驱动器，读通道驱动器和布置在HDA上的第一输入/输出（I / O）接口 PCB。 应用PCB包括执行应用和硬盘驱动器控制相关处理的专用集成电路和处理器中的至少一个。 缓冲器存储应用程序和硬盘驱动器控制相关数据。 在应用PCB上布置了硬盘驱动器控制器（HDC），映射驱动器和第二I / O接口。 第二个I / O接口与第一个I / O接口进行通信。 映射驱动器能够将逻辑地址映射到物理地址和监视读/写头的位置中的至少一个。

公开(公告)号：US20170228328A1

公开(公告)日：2017-08-10

申请号：US15424343

申请日：2017-02-03

申请人： Alan Armstrong ,  Bernie Sardinha

发明人： Alan Armstrong ,  Bernie Sardinha

IPC分类号： G06F13/16 ,  G06F1/26 ,  G06F12/02 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/1673 ,  G06F12/0246 ,  G06F13/4022 ,  G06F13/4081 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7205 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A method and apparatus for configuring or fabricating a small form-factor (“SFP”) non-volatile memory (“NVM”) solid state drive (“SSD”) plug is disclosed. The SFP NVM SSD (“SNS”) plug capable of storing data persistently, in one embodiment, is configured to couple to an SFP socket of a digital processing system capable of accessing external storage. The SFP socket is capable of providing memory access and optical communication. The SNS plug includes a connector, interface module, memory controller, buffer, and NVM chip wherein the digital processing system host performs storage access to the NVM chip via the memory controller.

公开(公告)号：US20080144821A1

公开(公告)日：2008-06-19

申请号：US11586860

申请日：2006-10-26

申请人： Alan Armstrong

发明人： Alan Armstrong

IPC分类号： H04N7/167

CPC分类号： H04N21/4408 ,  H04L63/0428 ,  H04N7/1675 ,  H04N21/43622 ,  H04N21/4367 ,  H04N21/4385 ,  H04N21/4405 ,  H04N21/4623 ,  H04N21/64322

摘要： Apparatus having corresponding methods, business methods, and computer programs comprises an input circuit to receive packets of encrypted encoded video data from a network; a storage device to store the encrypted encoded video data; a retrieve circuit to retrieve the encrypted encoded video data from the storage device; a decrypt circuit to decrypt the encrypted encoded video data into encoded video data while the retrieve circuit retrieves the encrypted encoded video data from the storage device; and an output circuit to transmit a signal representing the encoded video data while the decrypt circuit decrypts the encrypted encoded video data.

摘要翻译： 具有相应方法，业务方法和计算机程序的装置包括从网络接收加密的编码视频数据的分组的输入电路; 存储装置，用于存储加密的编码视频数据; 检索电路，用于从存储装置检索加密的编码视频数据; 解密电路，用于在所述检索电路从所述存储装置检索所述经加密的编码视频数据时将所述加密的编码视频数据解密为编码视频数据; 以及输出电路，用于在解密电路解密加密的编码视频数据的同时发送表示编码视频数据的信号。

公开(公告)号：US20120203921A1

公开(公告)日：2012-08-09

申请号：US13447486

申请日：2012-04-16

申请人： Alan Armstrong

发明人： Alan Armstrong

IPC分类号： G06F15/16

CPC分类号： G06F3/0674 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0676 ,  G06F12/00

摘要： A system including a network interface module, a first processor, a hard disk control module, and a second processor. The network interface module is configured to communicate with a network. The first processor is configured to (i) communicate with the network interface module, and (ii) perform processing related to communication of a hard disk drive with the network via the network interface module. The hard disk control module is configured to (i) communicate with the first processor, and (ii) control operation of the hard disk drive. The second processor is configured to (i) communicate with the hard disk control module, and (ii) perform processing related to storing data on the hard disk drive. The second processor and the hard disk control module are configured processes packets communicated via the network interface module using a hyper-text transfer protocol, a peer-to-peer sharing protocol, and an Internet protocol-based small computer system interface standard.

摘要翻译： 一种包括网络接口模块，第一处理器，硬盘控制模块和第二处理器的系统。 网络接口模块被配置为与网络通信。 第一处理器被配置为（i）与网络接口模块通信，以及（ii）经由网络接口​​模块执行与网络通信硬盘驱动器的处理。 硬盘控制模块被配置为（i）与第一处理器通信，以及（ii）控制硬盘驱动器的操作。 第二处理器被配置为（i）与硬盘控制模块通信，以及（ii）执行与在硬盘驱动器上存储数据有关的处理。 第二处理器和硬盘控制模块被配置为处理通过网络接口模块使用超文本传输​​协议，对等共享协议和基于因特网协议的小型计算机系统接口标准传送的分组。

公开(公告)号：US20120042056A1

公开(公告)日：2012-02-16

申请号：US13245269

申请日：2011-09-26

申请人： Alan Armstrong

发明人： Alan Armstrong

IPC分类号： G06F15/177

CPC分类号： G06F3/0674 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/0626 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0676 ,  G06F12/00

摘要： A system including a network interface module, a first processor, a hard disk control module, and a second processor. The network interface module is configured to communicate with a network. The first processor is configured to communicate with the network interface module and perform processing related to communication of a hard disk drive with the network via the network interface module. The hard disk control module is configured to communicate with the first processor and control operation of the hard disk drive. The second processor is configured to communicate with the hard disk control module and perform processing related to storing data on the hard disk drive. The second processor and the hard disk control module are configured to process packets communicated via the network interface module using a hyper-text transfer protocol, a peer-to-peer sharing protocol, and an Internet protocol-based small computer system interface standard.

摘要翻译： 一种包括网络接口模块，第一处理器，硬盘控制模块和第二处理器的系统。 网络接口模块被配置为与网络通信。 第一处理器被配置为与网络接口模块进行通信，并通过网络接口模块执行与网络通信硬盘驱动器的处理。 硬盘控制模块被配置为与第一处理器通信并控制硬盘驱动器的操作。 第二处理器被配置为与硬盘控制模块进行通信，并执行与在硬盘驱动器上存储数据有关的处理。 第二处理器和硬盘控制模块被配置为使用超文本传输​​协议，对等共享协议和基于因特网协议的小型计算机系统接口标准来处理经由网络接口​​模块传送的分组。