A semiconductor memory device includes a semiconductor substrate having a surface defining a plane extending substantially parallel thereto. A multiplicity of memory cells disposed on the substrate each have a selection transistor disposed in the plane. The transistor has a gate terminal and first and second electrode terminals. Each of the memory cells has a storage capacitor associated with and triggerable by the transistor. The capacitor has a ferroelectric dielectric and first and second capacitor electrodes. The capacitor has a configuration projecting upward from the plane and is disposed inside a trench extending as far as the second electrode terminal of the transistor. A word line is connected to the gate terminal of the transistor, a bit line is connected to the first electrode terminal of the transistor, and a common conductor layer of electrically conductive material is connected to the first capacitor electrode of the capacitor. A method for producing the device includes producing the capacitor after production of the transistor and metallizing layers associated with the transistor for connection of the word and bit lines, in a configuration projecting upward from the plane, and placing the capacitor inside a trench extending as far as the second electrode terminal of the transistor.