A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.