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公开(公告)号：US5877656A
公开(公告)日：1999-03-02
申请号：US865342
申请日：1997-05-29
申请人： Eric N. Mann , John Q. Torode
发明人： Eric N. Mann , John Q. Torode
摘要： A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
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公开(公告)号：US06433645B1
公开(公告)日：2002-08-13
申请号：US09048905
申请日：1998-03-26
申请人： Eric N. Mann , John Q. Torode
发明人： Eric N. Mann , John Q. Torode
IPC分类号： A03L700
摘要： A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
摘要翻译： 公开了一种用于产生时钟信号的可编程电路。 本发明提供了一种时钟发生器架构，其将基于PLL的时钟发生器电路与片上EPROM组合在单片时钟发生器芯片中。 时钟发生器允许电气配置各种信息，包括PLL参数，输入阈值，输出驱动电平和输出频率。 可以在制造时钟发生器之后配置各种参数。 参数可以在晶圆分类或包装后配置。 时钟发生器可以在打包之前被擦除，从而可以验证编程。
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公开(公告)号：US5835401A
公开(公告)日：1998-11-10
申请号：US760823
申请日：1996-12-05
申请人： Gary W. Green , John Q. Torode , T. J. Rodgers , Shailesh Shah
发明人： Gary W. Green , John Q. Torode , T. J. Rodgers , Shailesh Shah
IPC分类号： G11C11/406 , G11C11/24
CPC分类号： G11C11/406
摘要： A method and circuit for hiding a refresh of DRAM cells in a memory device. One embodiment of the circuit includes a selection circuit configured to select a first row of DRAM cells in the memory circuit in response to an active control signal. As a result, data may be read from or written to at least one of the DRAM cells in the first row. The selection circuit is also configured to couple a refresh address to a second row of DRAM cells in the memory circuit in response to an inactive state control signal. The second row of cells is refreshed when the selection circuit accesses the second row. For one embodiment, the DRAM cells are four transistor DRAM cells.
摘要翻译： 一种用于将DRAM单元的刷新隐藏在存储器件中的方法和电路。 电路的一个实施例包括选择电路，其被配置为响应于主动控制信号选择存储器电路中的第一行DRAM单元。 结果，数据可以从第一行的DRAM单元中的至少一个读取或写入。 选择电路还被配置为响应于非活动状态控制信号将刷新地址耦合到存储器电路中的第二行DRAM单元。 当选择电路访问第二行时，第二行单元格被刷新。 对于一个实施例，DRAM单元是四个晶体管DRAM单元。
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公开(公告)号：US5684434A
公开(公告)日：1997-11-04
申请号：US549915
申请日：1995-10-30
申请人： Eric N. Mann , John Q. Torode
发明人： Eric N. Mann , John Q. Torode
摘要： A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.
摘要翻译： 公开了一种用于产生时钟信号的可编程电路。 本发明提供了一种时钟发生器架构，其将基于PLL的时钟发生器电路与片上EPROM组合在单片时钟发生器芯片中。 时钟发生器允许电气配置各种信息，包括PLL参数，输入阈值，输出驱动电平和输出频率。 可以在制造时钟发生器之后配置各种参数。 参数可以在晶圆分类或包装后配置。 时钟发生器可以在打包之前被擦除，从而可以验证编程。
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