To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.