发明授权
- 专利标题: Flash memory array and decoding architecture
- 专利标题(中): 闪存阵列和解码架构
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申请号: US884926申请日: 1997-06-30
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公开(公告)号: US5856942A公开(公告)日: 1999-01-05
- 发明人: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人: Peter Wung Lee , Fu-Chang Hsu , Hsing-Ya Tsao
- 申请人地址: CA Santa Clara
- 专利权人: Aplus Integrated Circuits, Inc.
- 当前专利权人: Aplus Integrated Circuits, Inc.
- 当前专利权人地址: CA Santa Clara
- 主分类号: G11C11/56
- IPC分类号: G11C11/56 ; G11C16/08 ; G11C16/14 ; G11C16/16 ; G11C16/30 ; G11C16/34 ; H01L27/115 ; G11C11/34
摘要:
A flash memory circuit having a word line decoder with even and odd word line latches and a source line decoder with a source line latch is disclosed. The word line decoders and source line decoder provide the capability of erasing the memory cells of two adjacent word lines in a flash memory simultaneously and verifying the memory cells word line by word line. By erasing two adjacent rows simultaneously, the embodiments of this invention eliminate over-erasure and source disturbance problems associated with conventional flash memory circuits. The decoding architecture provides flexible erase size that can be from a pair to a large number of multiple pairs of word lines. By dividing the memory cells of a word line into a number of segments, the decoding circuit further provides the capability of selecting the memory cells of a word line segment for erasing.
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