The present invention supplies a first delay control signal generated by a DLL circuit to a first variable delay circuit which generates a control clock by delaying a clock for a prescribed time period. The DLL circuit comprises: a first delay loop, comprising a second variable delay circuit and a third variable delay circuit connected in series, to which the clock is supplied; a phase comparator which is supplied with a clock which delays an integral factor of 360.degree. of said clock from the clock, as a reference clock, and the output of the first delay loop, as a variable clock; and a delay control circuit which generates said first delay control signal in accordance with a phase comparison result signal from the phase comparator such that there is no phase difference with said two supplied clocks. The second variable delay circuit is supplied with the first delay control signal. The third variable delay circuit has a delay time of .beta..degree. in accordance with a second delay control signal generated by a .beta..degree. detecting circuit. As a result, the second variable delay circuit generates a delay time of approximately 360.degree.-.beta..degree.=.alpha..degree.. By similarly controlling the delay time of the first variable delay circuit by means of this first delay control signal, the control clock output therefrom is phase delayed by .alpha..degree. from the clock.