发明授权
- 专利标题: Semiconductor memory having redundancy circuit
- 专利标题(中): 具有冗余电路的半导体存储器
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申请号: US938962申请日: 1997-09-26
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公开(公告)号: US5983358A公开(公告)日: 1999-11-09
- 发明人: Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
- 申请人: Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
- 申请人地址: JPX Tokyo JPX Tokyo JPX Mobara
- 专利权人: Hitachi, Ltd.,Hitachi Ulsi Engineering Corp.,Hitachi Device Engineering Co., Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Ulsi Engineering Corp.,Hitachi Device Engineering Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo JPX Mobara
- 优先权: JPX8-255831 19960927
- 主分类号: G11C11/401
- IPC分类号: G11C11/401 ; G06F11/00 ; G11C29/00 ; G11C29/04
摘要:
A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
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