公开(公告)号：US5983358A

公开(公告)日：1999-11-09

申请号：US938962

申请日：1997-09-26

申请人： Masashi Horiguchi ,  Shinichi Miyatake ,  Tathunori Mushya ,  Yasuhiro Kasama ,  Yoichi Matsuno ,  Yasushi Kawase ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Shinichi Miyatake ,  Tathunori Mushya ,  Yasuhiro Kasama ,  Yoichi Matsuno ,  Yasushi Kawase ,  Yoshinobu Nakagome

IPC分类号： G11C11/401 ,  G06F11/00 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/842

摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.

摘要翻译： 具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元， 并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。 当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。

公开(公告)号：US5596535A

公开(公告)日：1997-01-21

申请号：US267267

申请日：1994-06-28

申请人： Tathunori Mushya ,  Masayasu Kawamura ,  Shunichi Sukegawa

发明人： Tathunori Mushya ,  Masayasu Kawamura ,  Shunichi Sukegawa

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/80 ,  G11C29/84

摘要： A semiconductor storage device equipped with redundant circuits designed to increase the operating speed and to simplify the layout by providing for the detection of the storage of a faulty address and access to the faulty address so as to substitute a spare word line for a faulty word line. The semiconductor storage device includes a MOSFET for causing current to flow through a pair of fuse means by a complementary address signal at one end of a fuse means corresponding to each bit of the faulty address. The other end thereof is connected to a wired OR logic so as to generate a decision signal. The fuse means corresponding to the MOSFET which is turned on by the faulty address signal is cut off to store a faulty address. The faulty address storage and comparison units can be formed with the pair of fuses and the MOSFET. High-speed operation and a high-density layout in the form of a matrix can thus be achieved efficiently by switching the faulty circuit to a spare circuit while the normal decoder is operating.

摘要翻译： 一种装备有冗余电路的半导体存储装置，其设计用于通过提供对故障地址的存储的检测和对故障地址的访问来提高操作速度和简化布局，以便将备用字线替换为有缺陷的字线 。 半导体存储装置包括用于使电流通过对应于故障地址的每个位的熔丝装置的一端的互补地址信号流过一对熔丝装置的MOSFET。 其另一端连接到有线OR逻辑，以产生判定信号。 对应于通过故障地址信号导通的MOSFET的熔丝装置被切断以存储故障地址。 故障地址存储和比较单元可以由一对保险丝和MOSFET形成。 因此，在通常的解码器工作时，通过将故障电路切换到备用电路，能够有效地实现矩阵形式的高速运转和高密度布局。