利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

218 条记录 (耗时 0.041 秒)

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06747509B2

    公开(公告)日：2004-06-08

    申请号：US10045105

    申请日：2002-01-15

    申请人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

    发明人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

    IPC分类号： G05F110

    CPC分类号： G11C8/08 ,  G11C5/14 ,  G11C5/147 ,  H01L2924/0002 ,  H01L2924/00

    摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

    摘要翻译： 可以减小副电源线上的电压降，以降低亚阈值电流，从而防止逻辑电路的工作速度降低。 主电源线沿着包括其亚阈值电流必须减小的MOS逻辑电路的矩形区域的一侧布置，并且在垂直于主电源线的方向上的区域上布置多个子电源线。 用于将副电源线选择性地电连接到主电源线的多个开关MOS晶体管相对于主电源线分散布置。 通过相对于主电源线分散配置开关MOS晶体管，与在一个地方设置开关MOS晶体管的情况相比，可以降低副电源线的等效电阻。

    Semiconductor integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit 有权

    公开(公告)号：US06339358B1

    公开(公告)日：2002-01-15

    申请号：US09513929

    申请日：2000-02-28

    申请人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

    发明人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

    IPC分类号： G05F110

    CPC分类号： G11C8/08 ,  G11C5/14 ,  G11C5/147 ,  H01L2924/0002 ,  H01L2924/00

    摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.

    High speed access compatible memory module
    7.
    发明授权
    High speed access compatible memory module 有权
    高速存取兼容内存模块

    公开(公告)号：US06438014B2

    公开(公告)日：2002-08-20

    申请号：US09803148

    申请日：2001-03-12

    申请人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

    发明人： Seiji Funaba ,  Yoshinobu Nakagome ,  Masashi Horiguchi ,  Yoji Nishio

    IPC分类号： G11C506

    CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  H01L23/5387 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2924/01055 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011

    摘要： A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

    摘要翻译： 模块基板具有与多个存储器芯片中的各个芯片数据端子相关联地分别设置的多个模块数据端子对，以及分别连接在多个模块数据端子对之间的多个模块数据布线。 多个模块数据布线连接到它们对应的芯片数据终端，并被配置为可用作存储器访问数据总线。 在并行布置多个存储器模块的存储器系统中，各个存储器模块的模块数据布线以串行形式连接，并且每个单独的模块数据配线不构成相对于数据的分支布线 总线在内存系统的主板上。 在存储器模块中，确保与存储器访问数据总线的宽度相对应的位数的并行访问。

    Ferroelectric memory
    8.
    发明授权
    Ferroelectric memory 失效
    铁电存储器

    公开(公告)号：US5539279A

    公开(公告)日：1996-07-23

    申请号：US362239

    申请日：1994-12-22

    申请人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

    发明人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Katsumi Matsuno ,  Takeshi Sakata ,  Jun Etoh ,  Yoshinobu Nakagome

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： A highly reliable and high speed ferroelectric memory having a high degree of integration. In a ferroelectric memory having a multiple of memory cells M1, each constituted by one transistor and one ferroelectric capacitor, in the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage on a storage node ST1 stores information in a DRAM mode. Both the electric potential at the plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are Vcc/2. When the a power supply voltage is turned on, a polarization state is detected as a ferroelectric memory of a plate electric potential of Vcc/2 and a precharge electric potential of Vss (or Vcc) and the read operation is performed a FERAM mode. The switching between the DRAM mode and the FERAM mode is executed by generating a signal to designate the FERAM mode in the memory along with the turn-on of the power supply and by generating a signal to designate the DRAM mode after completion of the conversion operation from nonvolatile information to volatile information.

    摘要翻译： 具有高度集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中，在正常操作中，铁电存储器用作其中存储节点ST1上的电压将信息存储在DRAM中的易失性存储器 模式。 强电介质电容器的板PL1的电位和数据线DL1（j）的预充电电位都为Vcc / 2。 当电源电压接通时，偏振状态被检测为Vcc / 2的电位电压和Vss（或Vcc）的预充电电位的铁电存储器，并且读取操作被执行FERAM模式。 DRAM模式和FERAM模式之间的切换通过产生一个信号来指示存储器中的FERAM模式以及电源的导通，并且在完成转换操作之后产生指定DRAM模式的信号 从非易失性信息到易失性信息。

    Semiconductor memory having error correcting means
    10.
    发明授权
    Semiconductor memory having error correcting means 失效
    具有误差校正装置的半导体存储器

    公开(公告)号：US4726021A

    公开(公告)日：1988-02-16

    申请号：US853230

    申请日：1986-04-17

    申请人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    发明人： Masashi Horiguchi ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi

    IPC分类号： G06F11/10 ,  G11C29/24 ,  G01R31/28

    CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G11C29/24

    摘要： A semiconductor memory having an error correcting function is provided, which has a device by which the user finds no difficulty in making use of the semiconductor memory and can test it with ease. In the semiconductor memory, a signal indicative of the completion of the preparation for reading/writing is outputted from the memory so that the user, after detecting the output of this signal, performs reading/writing data. To facilitate tests, such as a memory cell test for a redundant bit (check bit), an encoding circuit test and a decoding circuit test, the present invention provides that the arranged tests can be made independently of each other.

    摘要翻译： 提供了具有纠错功能的半导体存储器，其具有用户不用利用半导体存储器并且可以容易地进行测试的装置。 在半导体存储器中，从存储器输出表示完成读/写准备的信号，使得用户在检测到该信号的输出之后，执行读/写数据。 为了便于诸如用于冗余位（校验位）的存储器单元测试，编码电路测试和解码电路测试的测试，本发明提供了可以彼此独立地进行布置的测试。