发明授权
US5994933A Semiconductor device for controlling a delay time of an output signal of
a PLL
失效
用于控制PLL的输出信号的延迟时间的半导体器件
- 专利标题: Semiconductor device for controlling a delay time of an output signal of a PLL
- 专利标题(中): 用于控制PLL的输出信号的延迟时间的半导体器件
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申请号: US790016申请日: 1997-01-28
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公开(公告)号: US5994933A公开(公告)日: 1999-11-30
- 发明人: Tadao Yamanaka , Shinichi Nakagawa
- 申请人: Tadao Yamanaka , Shinichi Nakagawa
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha,Mitsubishi Electric Engineering Co., Ltd.
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha,Mitsubishi Electric Engineering Co., Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX8-225175 19960827
- 主分类号: G11C11/4076
- IPC分类号: G11C11/4076 ; H03H7/30 ; H03K3/03 ; H03K3/354 ; H03K5/14 ; H03L7/08 ; H03L7/081 ; H03L7/099 ; H03B27/00
摘要:
It is an object to obtain a semiconductor device capable of changing a delay time of an output signal of a PLL circuit with respect to an external clock signal after installed in a system. An external clock signal is inputted to an input terminal (1.) An address value is inputted to an input terminal (3.) A decoder (9) selects one of a plurality of delay times in a voltage-controlled oscillator (8) according to the address value. The phase of a signal outputted to an output terminal (2) is delayed with respect to the external clock signal at the input terminal (1) by the delay time selected. Accordingly, it is possible to change the delay time of the output signal of the PLL circuit with respect to the external clock signal after installation in a system.
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