Invention Grant
- Patent Title: Clock generation circuit for analog value memory circuit
- Patent Title (中): 模拟值存储电路的时钟发生电路
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Application No.: US205200Application Date: 1998-12-04
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Publication No.: US5999462APublication Date: 1999-12-07
- Inventor: Masayuki Katakura , Masashi Takeda
- Applicant: Masayuki Katakura , Masashi Takeda
- Applicant Address: JPX
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JPX
- Priority: JPXP08-057299 19960314; JPXP08-062255 19960319
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C27/04 ; G11C7/00
Abstract:
An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
Public/Granted literature
- US5425515A Aircraft Public/Granted day:1995-06-20
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