Clock generation circuit for analog value memory circuit
    1.
    发明授权
    Clock generation circuit for analog value memory circuit 失效
    模拟值存储电路的时钟发生电路

    公开(公告)号:US5999462A

    公开(公告)日:1999-12-07

    申请号:US205200

    申请日:1998-12-04

    IPC分类号: G11C7/22 G11C27/04 G11C7/00

    CPC分类号: G11C7/222 G11C27/04 G11C7/22

    摘要: An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

    摘要翻译: 一种包括模拟存储电路的模拟延迟电路,其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵,包括为各个列提供的行开关,用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 将X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数设置为除了1以外没有公共除数。因此,当要选择性地扫描存储器单元时, 可以在不依赖于存储单元的位置的情况下向所有存储单元提供相同的选择条件,并且减少连接到信号写/读终端的寄生电容。

    Digital-to-analog converting system
    2.
    发明授权
    Digital-to-analog converting system 失效
    数模转换系统

    公开(公告)号:US4739304A

    公开(公告)日:1988-04-19

    申请号:US917308

    申请日:1986-10-10

    IPC分类号: H03M1/00 H03M1/68 H03M1/82

    CPC分类号: H03M1/68 H03M1/745 H03M1/822

    摘要: A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.

    摘要翻译: 数模转换器将输入数字信号分为最低有效位组和最高有效位组。 使用脉冲幅度调制转换最高有效位组,并且使用脉冲宽度调制转换最低有效位组,其中脉冲宽度在转换周期内关于预定时间点对称地改变,以便提高脉冲宽度的线性 调制转换。

    Analog value memory circuit
    3.
    发明授权
    Analog value memory circuit 失效
    模拟值存储电路

    公开(公告)号:US6104626A

    公开(公告)日:2000-08-15

    申请号:US808866

    申请日:1997-02-28

    IPC分类号: G11C7/22 G11C27/04 G11C27/00

    CPC分类号: G11C7/222 G11C27/04 G11C7/22

    摘要: An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.

    摘要翻译: 一种包括模拟存储电路的模拟延迟电路,其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵,包括为各个列提供的行开关,用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数被设置为使得它们除了1之外没有公共除数。因此,当要选择性地扫描存储器单元时, 可以在不依赖于存储单元的位置的情况下,向所有存储单元提供相同的选择条件,并且减少连接到信号写入/读取端子的寄生电容。

    Information providing system, information providing device, and system for controlling robot device
    4.
    发明授权
    Information providing system, information providing device, and system for controlling robot device 失效
    信息提供系统,信息提供装置和控制机器人装置的系统

    公开(公告)号:US07318044B2

    公开(公告)日:2008-01-08

    申请号:US09958408

    申请日:2001-02-09

    IPC分类号: G06Q30/00

    摘要: The present invention makes it possible and easier to serve optimum robot components/devices/accessories by means of an information service system including personal terminal devices (31A to 31C) connected to an information communication network via a telecommunication line, and a server (38) connected to the information communication network via the telecommunication line to cumulatively store information on components/devices/accessories available from a plurality of manufacturers (37a, 37c and 37c) (third party) of components/devices/accessories of a robot 1, as classified according to the attributes of the components/devices/accessories and send, to the personal terminal devices (31A to 31C) connected thereto, options information prepared based on the attribute of the cumulatively stored components/devices/accessories information and including a plurality of items for selection of a robot component.

    摘要翻译: 本发明使得通过包括经由电信线路连接到信息通信网络的个人终端设备(31A至31C)的信息服务系统和服务器(...),可以更容易地为最佳机器人部件/设备/附件提供服务 38),其经由电信线路连接到信息通信网络,以累积地存储可从多个制造商(37a,37c和37c)(第三方)获得的组件/设备/附件的信息 机器人1,根据组件/设备/附件的属性分类并发送到与其相连的个人终端设备(31A至31C),基于累积存储的组件/设备/附件的属性准备的选项信息 信息,并且包括用于选择机器人部件的多个项目。

    Processing method and system of data management for IC card
    5.
    发明申请
    Processing method and system of data management for IC card 审中-公开
    IC卡数据管理的处理方法和系统

    公开(公告)号:US20050038820A1

    公开(公告)日:2005-02-17

    申请号:US10951958

    申请日:2004-09-27

    IPC分类号: G07F7/10 G06F7/00

    摘要: A method and a system wherein IC card information can be changed in either of two ways is provided. The information stored in an IC card can be changed independently of the information that a center facility maintains, and then the corresponding IC card information maintained by the center facility is updated to reflect the changes made in the IC card. Alternatively, the IC card information maintained in the center facility is changed, and then the corresponding information in the IC card is updated to reflect those changes.

    摘要翻译: 提供了一种方法和系统,其中可以以两种方式之一来改变IC卡信息。 存储在IC卡中的信息可以独立于中心设备维护的信息进行更改,然后更新由中心设备维护的相应IC卡信息,以反映IC卡中所做的更改。 或者,改变保存在中心设施中的IC卡信息,然后更新IC卡中的相应信息以反映这些变化。

    Processing method and system of data management for IC card
    6.
    发明授权
    Processing method and system of data management for IC card 失效
    IC卡数据管理的处理方法和系统

    公开(公告)号:US06805296B2

    公开(公告)日:2004-10-19

    申请号:US09896933

    申请日:2001-06-28

    IPC分类号: G06K1900

    摘要: In accordance with the invention, a method and system is provided wherein IC card information can be changed in either of two ways: (1) the information stored in IC card is changed independently of the information that the center facility maintains, and then the corresponding IC card information maintained by the center facility is updated to reflect the changes made in the IC card, and (2) the IC card information maintained in the center apparatus is changed, and then the corresponding information in the IC card is updated to reflect the changes made in the center apparatus.

    摘要翻译: 根据本发明,提供了一种方法和系统,其中IC卡信息可以通过以下两种方式之一改变:(1)存储在IC卡中的信息独立于中心设备维护的信息而改变,然后相应地 更新由中心设备维护的IC卡信息以反映IC卡中所做的更改,(2)改变中心设备中保存的IC卡信息,然后更新IC卡中的对应信息,以反映 中心设备改变。

    Piston for an internal combustion engine
    8.
    发明授权
    Piston for an internal combustion engine 失效
    内燃机活塞

    公开(公告)号:US5487364A

    公开(公告)日:1996-01-30

    申请号:US216981

    申请日:1994-03-23

    IPC分类号: F02F3/00 F16J1/04

    CPC分类号: F02F3/00 F05C2201/021

    摘要: A piston for an internal combustion engine includes a skirt portion configured so that a value S/(D * L) is in the range of 0.4-0.55, where L is a length of the skirt portion, D is a diameter of a cylinder bore, and S is an area of an image of the skirt portion when the skirt portion is projected onto a plane perpendicular to a direction connecting a pair of boss portions. This condition decreases the friction between the piston and the cylinder bore.

    摘要翻译: 用于内燃机的活塞包括裙部,其构造成使得S /(D * L)的值在0.4-0.55的范围内,其中L是裙部的长度,D是缸孔的直径 S是当裙部突出到与连接一对凸起部的方向垂直的平面上时的裙部的图像的区域。 这种情况会降低活塞和气缸孔之间的摩擦。

    Double-sided logic input differential switch
    9.
    发明授权
    Double-sided logic input differential switch 失效
    双面逻辑输入差分开关

    公开(公告)号:US4714841A

    公开(公告)日:1987-12-22

    申请号:US748596

    申请日:1985-06-25

    CPC分类号: H03K3/2885 H03K19/086

    摘要: A logic circuit adapted for fabrication as an integrated circuit is formed having a differential amplifier operating with a constant current source and an appropriate voltage source, and having output transistors to provide the necessary output voltages, does not require a reference voltage input to the differential amplifier, thus, reference voltage transistors are not required. The two binary input signals are selected to have the same amplitude difference between the high and low levels thereof and one of the two input signals is shifted relative to the other one by the amount substantially equal to 1/2 the selected amplitude difference, and the output signals are similarly level shifted. Using this basic logic circuit as a building block other, more complex, logic circuits can be obtained.

    摘要翻译: 适用于作为集成电路制造的逻辑电路形成为具有用恒定电流源和适当电压源工作的差分放大器,并且具有输出晶体管以提供必要的输出电压,不需要将参考电压输入到差分放大器 因此,不需要参考电压晶体管。 选择两个二进制输入信号在其高电平和低电平之间具有相同的幅度差,并且两个输入信号中的一个相对于另一个输入信号相移大约等于所选择的幅度差的1/2, 输出信号类似地电平移位。 使用该基本逻辑电路作为构建块,可以获得更复杂的逻辑电路。

    Analog-to-digital converter
    10.
    发明授权
    Analog-to-digital converter 失效
    模数转换器

    公开(公告)号:US4599599A

    公开(公告)日:1986-07-08

    申请号:US400058

    申请日:1982-07-20

    IPC分类号: H03M1/00 H03K5/153

    CPC分类号: H03M1/361

    摘要: An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes at least 2.sup.m+n -1 resistors connected in a series circuit to a voltage source for establishing respective reference voltages; switch elements selectively coupled to the analog input signal and the resistors in response to a switch control signal for supplying a signal indicative of the analog input signal and the respective reference voltages; at least 2.sup.m -1 upper bit comparators for generating the switch control signal and output signals indicative of the m upper bits, with first inputs receiving the analog input signal and second inputs connected to the series circuit at intervals defining groups of the resistors; an upper bit encoder receiving the output signals from the upper bit comparators and generating the m upper bits; at least 2.sup.n -1 lower bit comparators for generating output signals indicative of the n lower bits, having first and second inputs connected to the switch elements whereby the switch elements selectively supply the signal indicative of the analog input signal to the first inputs and selectively connect the second inputs to the respective resistors in response to the switch control signal; and a lower bit encoder receiving the output signal from the lower bit comparators for generating the n lower bits.

    摘要翻译: 用于将模拟输入信号转换为具有m个高位和n个低位的数字输出信号的模数转换器包括连接到电压源的串联电路中的至少2m + n-1个电阻器,用于建立相应的参考电压; 响应于用于提供指示模拟输入信号和各个参考电压的信号的开关控制信号,选择性地耦合到模拟输入信号和电阻器的开关元件; 至少2m-1个高位比较器,用于产生开关控制信号和输出指示m个高位的信号,其中第一输入接收模拟输入信号,第二输入以限定电阻器组的间隔连接到串联电路; 高位编码器接收来自高位比较器的输出信号并产生m位高位; 至少2n-1个低位比较器,用于产生指示n个较低位的输出信号,具有连接到开关元件的第一和第二输入,由此开关元件选择性地将指示模拟输入信号的信号提供给第一输入并选择性地连接 响应于所述开关控制信号对所述各个电阻器的第二输入; 以及下位编码器,接收来自下位比较器的输出信号,用于产生n个较低位。