摘要:
An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要:
A digital-to-analog convertor divides an input digital signal into a least significant bit group and a most significant bit group. The most significant bit group is converted using pulse amplitude modulation and the least significant bit group is converted using pulse width modulation, in which the pulse widths are varied symmetrically about predetermined time points within a conversion period in order to improve the linearity of the pulse width modulation conversion.
摘要:
An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要:
The present invention makes it possible and easier to serve optimum robot components/devices/accessories by means of an information service system including personal terminal devices (31A to 31C) connected to an information communication network via a telecommunication line, and a server (38) connected to the information communication network via the telecommunication line to cumulatively store information on components/devices/accessories available from a plurality of manufacturers (37a, 37c and 37c) (third party) of components/devices/accessories of a robot 1, as classified according to the attributes of the components/devices/accessories and send, to the personal terminal devices (31A to 31C) connected thereto, options information prepared based on the attribute of the cumulatively stored components/devices/accessories information and including a plurality of items for selection of a robot component.
摘要:
A method and a system wherein IC card information can be changed in either of two ways is provided. The information stored in an IC card can be changed independently of the information that a center facility maintains, and then the corresponding IC card information maintained by the center facility is updated to reflect the changes made in the IC card. Alternatively, the IC card information maintained in the center facility is changed, and then the corresponding information in the IC card is updated to reflect those changes.
摘要:
In accordance with the invention, a method and system is provided wherein IC card information can be changed in either of two ways: (1) the information stored in IC card is changed independently of the information that the center facility maintains, and then the corresponding IC card information maintained by the center facility is updated to reflect the changes made in the IC card, and (2) the IC card information maintained in the center apparatus is changed, and then the corresponding information in the IC card is updated to reflect the changes made in the center apparatus.
摘要:
A cylinder head gasket is disposed between a cylinder head and a cylinder block having different coefficients of thermal expansion. The cylinder head gasket has a bore grommet including a cylinder block side portion which is enlarged in a direction away from the cylinder bore hole on an exhaust side and on an end opposite to a chain or gear casing end.
摘要:
A piston for an internal combustion engine includes a skirt portion configured so that a value S/(D * L) is in the range of 0.4-0.55, where L is a length of the skirt portion, D is a diameter of a cylinder bore, and S is an area of an image of the skirt portion when the skirt portion is projected onto a plane perpendicular to a direction connecting a pair of boss portions. This condition decreases the friction between the piston and the cylinder bore.
摘要:
A logic circuit adapted for fabrication as an integrated circuit is formed having a differential amplifier operating with a constant current source and an appropriate voltage source, and having output transistors to provide the necessary output voltages, does not require a reference voltage input to the differential amplifier, thus, reference voltage transistors are not required. The two binary input signals are selected to have the same amplitude difference between the high and low levels thereof and one of the two input signals is shifted relative to the other one by the amount substantially equal to 1/2 the selected amplitude difference, and the output signals are similarly level shifted. Using this basic logic circuit as a building block other, more complex, logic circuits can be obtained.
摘要:
An analog-to-digital converter for converting an analog input signal to a digital output signal with m upper bits and n lower bits includes at least 2.sup.m+n -1 resistors connected in a series circuit to a voltage source for establishing respective reference voltages; switch elements selectively coupled to the analog input signal and the resistors in response to a switch control signal for supplying a signal indicative of the analog input signal and the respective reference voltages; at least 2.sup.m -1 upper bit comparators for generating the switch control signal and output signals indicative of the m upper bits, with first inputs receiving the analog input signal and second inputs connected to the series circuit at intervals defining groups of the resistors; an upper bit encoder receiving the output signals from the upper bit comparators and generating the m upper bits; at least 2.sup.n -1 lower bit comparators for generating output signals indicative of the n lower bits, having first and second inputs connected to the switch elements whereby the switch elements selectively supply the signal indicative of the analog input signal to the first inputs and selectively connect the second inputs to the respective resistors in response to the switch control signal; and a lower bit encoder receiving the output signal from the lower bit comparators for generating the n lower bits.