A cache memory consists of plurality of memory bits within a random-access memory (RAM) cell. An extra address decode circuit is needed to select a single memory bit within the multi-bit RAM cell before normal access of RAM array circuit. Combining of multiple bits into a RAM cell reduces the number of interconnections in comparison to single bit RAM cell. This technique eliminates the need to break up the cache array into multiple sets for reducing power dissipation. The area advantages are also from optimal layout of multi-bit RAM cell, address decoder, and sense amplifier unit. Furthermore, the interconnections can be widened to reduce the RC delay as it is a dominating factor in future technology advancement. The multiplexing of the bits are done before the row decoding thus reducing one level of multiplexing after reading of data from the sense amplifier units.