发明授权
US6013574A Method of forming low resistance contact structures in vias arranged
between two levels of interconnect lines
失效
在布置在两层互连线之间的通孔中形成低电阻接触结构的方法
- 专利标题: Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines
- 专利标题(中): 在布置在两层互连线之间的通孔中形成低电阻接触结构的方法
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申请号: US906062申请日: 1997-08-05
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公开(公告)号: US6013574A公开(公告)日: 2000-01-11
- 发明人: Fred N. Hause , Michael J. Gatto , Kuang-Yeh Chang
- 申请人: Fred N. Hause , Michael J. Gatto , Kuang-Yeh Chang
- 申请人地址: CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: CA Sunnyvale
- 主分类号: H01L21/311
- IPC分类号: H01L21/311 ; H01L21/768 ; H01L21/28 ; H01L21/31
摘要:
A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure. Each resulting via is substantially void of polymer and oxide residue so as to present a clean via area which allows ready adherence of a plug material to the anti-reflective coating.
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