公开(公告)号：US6013574A

公开(公告)日：2000-01-11

申请号：US906062

申请日：1997-08-05

申请人： Fred N. Hause ,  Michael J. Gatto ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Michael J. Gatto ,  Kuang-Yeh Chang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L21/02063 ,  H01L21/31105 ,  H01L21/31138 ,  H01L21/76877

摘要： A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure. Each resulting via is substantially void of polymer and oxide residue so as to present a clean via area which allows ready adherence of a plug material to the anti-reflective coating.

摘要翻译： 提供了一种在布置在互连层之间的通孔中形成低电阻接触结构的方法。 该方法涉及在其上形成有抗反射层的互连线。 在互连线上形成层间电介质层。 在层间电介质层之上形成光致抗蚀剂层并图案化以限定通孔位置。 在通孔蚀刻期间，在通孔底部的抗反射涂覆的互连线上形成有机（碳基）聚合物层。 然后使用采用包含氮和氢的成形气体的干式蚀刻工艺除去光致抗蚀剂和蚀刻副产物聚合物层。 当暴露于氧气时，随后在抗反射涂布的互连线上形成天然氧化物层。 然后在溅射蚀刻过程期间将天然氧化物层与任何残留的蚀刻副产物聚合物一起除去。 每个所得到的通孔基本上不含聚合物和氧化物残余物，以便呈现干净的通孔区域，其允许插塞材料容易地粘附到抗反射涂层上。

公开(公告)号：US5811347A

公开(公告)日：1998-09-22

申请号：US641028

申请日：1996-04-29

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/314 ,  H01L21/318 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3144 ,  H01L21/3185 ,  H01L21/76224 ,  Y10S148/05

摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.sub.2 trench liner and subsequently implanting the SiO.sub.2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

摘要翻译： 一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。 改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。 在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。 此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。 接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。 随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。 然后形成沟槽衬垫，并且氮结合到沟槽衬里中。 通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。 在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。 此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

公开(公告)号：US5981357A

公开(公告)日：1999-11-09

申请号：US877000

申请日：1997-06-16

申请人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.

摘要翻译： 提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。 隔离过程产生具有增强的机械和电性能的硅台面。 通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。 通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。 图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。 图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

公开(公告)号：US5962914A

公开(公告)日：1999-10-05

申请号：US168761

申请日：1998-10-08

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L24/36

CPC分类号： H01L21/76213

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

公开(公告)号：US5937310A

公开(公告)日：1999-08-10

申请号：US639758

申请日：1996-04-29

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76213 ,  Y10S438/981

摘要： A method of forming a self-aligned field oxide isolation structure without using silicon nitride. The method comprises forming a dielectric on an upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate comprises an active region and an isolation region laterally adjacent to each other. A photoresist layer is patterned on top of the implant dielectric to expose regions of the implant dielectric over the active region. Nitrogen is then implanted into the active region through the implant dielectric. Nitrogen is preferably introduced into semiconductor substrate in an approximate atomic concentration of 0.5 to 2.0 percent. After the nitrogen has been implanted into a semiconductor substrate, the photoresist layer is stripped and the implant dielectric is removed. The wafer is then thermally oxidized such that a field oxide having a first thickness is grown over the isolation region and a thin oxide having a second thickness is grown over the active region. The presence of the nitrogen within the semiconductor substrate retards the oxidation rate of the silicon in the active region such that the thickness of the thin oxide is substantially less than the thickness of the thermal oxide. In a presently preferred embodiment, the field oxide has a thickness of 2,000 to 8,000 angstroms while the thin oxide has a thickness of less than 300 angstroms.

摘要翻译： 在不使用氮化硅的情况下形成自对准场氧化物隔离结构的方法。 该方法包括在半导体衬底的上表面上形成电介质。 半导体衬底的上表面包括相互横向相邻的有源区和隔离区。 在植入电介质的顶部上构图光致抗蚀剂层，以在有源区域上暴露植入电介质的区域。 然后通过植入电介质将氮注入有源区。 氮优选以0.5至2.0％的近似原子浓度引入半导体衬底。 在将氮气注入到半导体衬底中之后，剥离光致抗蚀剂层并除去注入电介质。 然后将晶片热氧化，使得具有第一厚度的场氧化物在隔离区上生长，并且在有源区上生长具有第二厚度的薄氧化物。 半导体衬底内的氮的存在阻碍了有源区中硅的氧化速率，使得薄氧化物的厚度基本上小于热氧化物的厚度。 在目前优选的实施例中，场氧化物的厚度为2,000至8,000埃，而薄氧化物的厚度小于300埃。

公开(公告)号：US5904539A

公开(公告)日：1999-05-18

申请号：US619004

申请日：1996-03-21

申请人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

发明人： Fred N. Hause ,  Robert Dawson ,  Charles E. May ,  Mark I. Gardner ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229 ,  Y10S148/05

摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.

摘要翻译： 提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。 隔离过程产生具有增强的机械和电性能的硅台面。 通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。 通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。 图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。 图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

公开(公告)号：US5643825A

公开(公告)日：1997-07-01

申请号：US366053

申请日：1994-12-29

申请人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

发明人： Mark I. Gardner ,  Fred N. Hause ,  Kuang-Yeh Chang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/762

摘要： An improved process is provided for forming field dielectric in lieu of local oxidation process often referred to as the "LOCOS" process. The improved process utilizes blanket formation of first and second dielectrics across an entire semiconductor substrate. In a subsequent step, both first and second dielectrics are selectively removed in areas overlying active regions. The first and second dielectrics are formed using a combination of thermal growth and/or chemical deposition. The resulting field dielectric structure is relatively thin, yet demonstrates superior dielectric properties. Blanket formation followed by select removal ensures a fine-line demarcation between field and active regions and substantially eliminates encroachment problems normally associated with conventional LOCOS. Additionally, the thin field dielectric structure can be formed with rounded or reflowed corners to avoid step coverage problems for subsequently placed conductive elements.

摘要翻译： 提供了用于形成场电介质以代替通常称为“LOCOS”工艺的局部氧化工艺的改进方法。 改进的方法利用穿过整个半导体衬底的第一和第二电介质的覆盖层形成。 在随后的步骤中，第一和第二电介质在覆盖有源区域的区域中被选择性地去除。 使用热生长和/或化学沉积的组合形成第一和第二电介质。 所得到的场介电结构相对较薄，但表现出优异的介电性能。 毯子形成，然后选择移除确保场和活动区域之间的细线划分，并且基本上消除通常与常规LOCOS相关联的侵入问题。 此外，薄场电介质结构可以形成为圆形或回流角，以避免随后放置的导电元件的步骤覆盖问题。

公开(公告)号：US08034712B2

公开(公告)日：2011-10-11

申请号：US12897073

申请日：2010-10-04

申请人： Kuang-Yeh Chang ,  Hong Ma

发明人： Kuang-Yeh Chang ,  Hong Ma

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.

摘要翻译： 描述了制造双镶嵌结构的方法。 介电层和金属硬掩模层依次形成在其上具有导电层和衬垫层的基板上。 将金属硬掩模层和电介质层图案化以形成露出衬垫层的一部分的通孔。 通孔中填充间隙填充层，其高度为通孔深度的1/4至1/2。 在金属硬掩模层和电介质层中形成沟槽。 去除间隙填充层以露出衬里层的部分，然后将其移除。 形成填充在通孔和沟槽中的金属层，然后去除金属硬掩模层。

公开(公告)号：US07030952B2

公开(公告)日：2006-04-18

申请号：US09683364

申请日：2001-12-19

申请人： Kuang-Yeh Chang ,  Kuo-Yun Kuo

发明人： Kuang-Yeh Chang ,  Kuo-Yun Kuo

IPC分类号： G02F1/1343

CPC分类号： G02F1/136 ,  G02F1/136277

摘要： A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

公开(公告)号：US06835584B2

公开(公告)日：2004-12-28

申请号：US10605897

申请日：2003-11-05

申请人： Kuang-Yeh Chang ,  Kuo-Yun Kuo

发明人： Kuang-Yeh Chang ,  Kuo-Yun Kuo

IPC分类号： H01L2100

CPC分类号： G02F1/136 ,  G02F1/136277

摘要： A plurality of active areas are defined on a semiconductor substrate. Then at least one gate is formed on the semiconductor substrate to cover a portion of the active area. Thereafter a plurality of source/drain are formed in the active area not covered by the gate followed by forming a first dielectric layer on the semiconductor substrate to cover the gate and the source/drain. After that, at least one pixel cap top plate is formed atop the first dielectric layer and a capacitor dielectric layer is formed atop the surface of the top plate. Finally, at least one pixel cap bottom plate is formed atop the first dielectric layer to cover the top plate.

摘要翻译： 多个有源区域被限定在半导体衬底上。 然后在半导体衬底上形成至少一个栅极以覆盖有源区的一部分。 此后，在未被栅极覆盖的有源区域中形成多个源极/漏极，随后在半导体衬底上形成覆盖栅极和源极/漏极的第一电介质层。 之后，在第一电介质层的顶部形成至少一个像素盖顶板，并且在顶板的表面顶部形成电容器电介质层。 最后，至少一个像素帽底板形成在第一介电层的顶部以覆盖顶板。