The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact to a node location comprising: a) forming an electrically insulative layer over a node location; b) patterning a masking layer over a portion of the insulative layer to form an unmasked portion and a masked portion of the insulative layer; c) removing parts of the masked and unmasked portions of the insulative layer to form a first opening over the node location which underlies a portion of the masking layer; d) forming an etch restriction layer within the first opening and over the masking layer; e) forming a sacrificial spacer layer within the first opening and over the etch restriction layer; f) forming a second opening extending from the first opening to the node location; and g) forming an electrically conductive pedestal within the first and second openings and in electrical connection with the node location. The invention also includes a capacitor comprising: a) an electrically conductive pedestal in electrical contact with a node location, the pedestal, viewed laterally in cross-section, comprising a pair of opposing lateral surfaces; b) an inner electrically conductive layer laterally against both lateral surfaces; c) a capacitor dielectric layer laterally against the inner conductive layer; and d) an outer electrically conductive layer laterally against the capacitor dielectric layer.