发明授权
- 专利标题: Method and system for arbitrating a bus according to the status of a buffer and destination information
- 专利标题(中): 根据缓冲区和目的地信息的状态仲裁总线的方法和系统
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申请号: US708324申请日: 1996-09-05
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公开(公告)号: US6021455A公开(公告)日: 2000-02-01
- 发明人: Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
- 申请人: Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX7-228231 19950905
- 主分类号: G06F13/36
- IPC分类号: G06F13/36 ; G06F13/362 ; G06F13/364 ; G06F13/00
摘要:
An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.
公开/授权文献
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