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    Information processing system, bus arbiter, and bus controlling method
    1.
    发明授权
    Information processing system, bus arbiter, and bus controlling method 有权
    信息处理系统，总线仲裁器和总线控制方法

    公开(公告)号：US06425037B1

    公开(公告)日：2002-07-23

    申请号：US09407064

    申请日：1999-09-28

    申请人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    发明人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    IPC分类号： G06F1300

    CPC分类号： G06F13/364

    摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. The present invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion means for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage means for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request when it performs an access operation, the bus arbiter refers to the access destination information and the data storage status of the storage means and decides whether or not to give a bus occupation right to the bus master.

    摘要翻译： 本发明提供了一种用于防止诸如通过具有低速IO接入的总线竞争阻塞的主存储访问的事务的执行并提高总线占用效率的手段。本发明包括第一总线，第二总线，多个 连接到两个总线的模块，用于在两个总线之间执行信息的协议转换的总线转换装置，用于仲裁总线主机的总线占用权请求的总线仲裁器，以及用于当存储访问数据达到预定量时存储访问数据的存储装置 访问目的地是预定模块。 每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存取装置的访问目的地信息和数据存储状态 并决定是否给予巴士总线职业权。

    Method and system for arbitrating a bus according to the status of a buffer and destination information
    2.
    发明授权
    Method and system for arbitrating a bus according to the status of a buffer and destination information 失效
    根据缓冲区和目的地信息的状态仲裁总线的方法和系统

    公开(公告)号：US6021455A

    公开(公告)日：2000-02-01

    申请号：US708324

    申请日：1996-09-05

    申请人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    发明人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.

    摘要翻译： 一种信息处理系统，包括第一总线，第二总线，连接到两个总线的多个模块，用于仲裁总线主机的总线访问请求的总线仲裁器，以及用于存储高达预定量的访问数据的存储装置， 当访问目的地信息指示所述模块是访问目的地时，模块之一。 每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断总线主机之一发出总线访问请求时，总线仲裁器是指预定量的访问目的地信息是否完全存储在存储器中 意味着，并决定是否给总线访问总线主控。

    Information processing system, bus arbiter, and bus controlling method
    3.
    发明授权
    Information processing system, bus arbiter, and bus controlling method 有权
    信息处理系统，总线仲裁器和总线控制方法

    公开(公告)号：US06584530B2

    公开(公告)日：2003-06-24

    申请号：US10173819

    申请日：2002-06-19

    申请人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    发明人： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

    IPC分类号： G06F1338

    CPC分类号： G06F13/364

    摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request, the bus arbiter refers to the access destination information and the data storage status of the storage and decides whether to give a bus occupation right to the bus master.

    摘要翻译： 本发明提供了一种用于防止执行诸如主存储器访问的事务的方法，以便通过具有低速IO访问的总线竞争阻塞，并且提高总线占用效率。用于防止执行诸如存储访问以避免总线阻塞的事务的装置 竞争与低速IO访问。 本发明包括第一总线，第二总线，连接到两个总线的多个模块，用于在两个总线之间执行信息协议转换的总线转换单元，用于仲裁总线主机的总线占用权请求的总线仲裁器和 存储器，用于当访问目的地是预定模块时存储高达预定量的访问数据。 每个总线主机输出接入目的地信息，当总线仲裁器判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存储的访问目的地信息和数据存储状态，并决定是否给出总线 占领权掌握公交车主。

    Information processor with snoop suppressing function, memory controller, and direct memory access processing method
    4.
    发明授权
    Information processor with snoop suppressing function, memory controller, and direct memory access processing method 失效
    具有窥探抑制功能的信息处理器，存储器控制器和直接存储器存取处理方法

    公开(公告)号：US06748463B1

    公开(公告)日：2004-06-08

    申请号：US09463599

    申请日：2000-06-22

    申请人： Masahide Tsuboi ,  Takashi Moriyama ,  Hiroshi Murashima ,  Masumi Terao ,  Michinori Naitoh ,  Koichi Okazawa ,  Masaya Umemura

    发明人： Masahide Tsuboi ,  Takashi Moriyama ,  Hiroshi Murashima ,  Masumi Terao ,  Michinori Naitoh ,  Koichi Okazawa ,  Masaya Umemura

    IPC分类号： G06F1314

    CPC分类号： G06F12/0835

    摘要： An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.

    摘要翻译： 具有分级总线结构的信息处理设备，其具有连接到中央处理单元和高速缓冲存储器的系统总线以及连接到I / O设备的I / O总线。 响应于来自I / O设备的DMA请求，连接到总线和主存储器的存储器控​​制器将存储在存储器控制器的缓冲存储器中的先前侦听地址与包含在DMA请求中的当前地址进行比较，以检查是否 当前的DMA请求与过去的窥探过程一致。 如果比较指示一致的窥探过程，则禁止窥探访问过程请求输出到系统总线和高速缓冲存储器。 通过该操作，可以减少DMA到高速缓冲存储器的同一块的窥探访问次数，并且可以缩短系统总线占用的时间，从而提高系统性能。

    ELECTRONIC DEVICE USING TOUCH PANEL INPUT AND METHOD FOR RECEIVING OPERATION THEREBY
    5.
    发明申请
    ELECTRONIC DEVICE USING TOUCH PANEL INPUT AND METHOD FOR RECEIVING OPERATION THEREBY 审中-公开
    使用触摸面板输入的电子设备及其接收操作的方法

    公开(公告)号：US20130082969A1

    公开(公告)日：2013-04-04

    申请号：US13700966

    申请日：2011-05-30

    申请人： Takashi Moriyama

    发明人： Takashi Moriyama

    IPC分类号： G06F3/01

    CPC分类号： G06F3/017 ,  G06F3/04842 ,  G06F3/0488

    摘要： Provided are a display, which displays a screen, and a touch panel, which is disposed on the display. In accordance with a series of consecutive operations by a user to the touch panel involving touch operation, drag operation, and release operation, the following are accepted: the selection of an action area from among one or more action areas displayed on the basis of a touched area on the touch panel at the time of a user's touch operation, and the execution of an action corresponding to the action area.

    摘要翻译： 提供了显示器，显示屏幕和布置在显示器上的触摸面板。 根据用户对触摸操作，拖动操作和释放操作的一系列连续操作，接受以下操作：从基于a的显示的一个或多个动作区域中选择动作区域 在用户的触摸操作时在触摸面板上触摸的区域，以及执行与动作区域相对应的动作。

    Organic electroluminescence display device
    7.
    发明授权
    Organic electroluminescence display device 失效
    有机电致发光显示装置

    公开(公告)号：US08242689B2

    公开(公告)日：2012-08-14

    申请号：US13197982

    申请日：2011-08-04

    申请人： Takashi Moriyama ,  Noriyuki Shikina ,  Nobuhiko Sato

    发明人： Takashi Moriyama ,  Noriyuki Shikina ,  Nobuhiko Sato

    IPC分类号： H01J1/62

    CPC分类号： H01L51/5275

    摘要： An organic electroluminescence display device includes a plurality of pixels and an array of lenses arranged thereupon. Each pixel includes a light emitting region provided with a lens and a light emitting region provided without a lens. The light emitting regions of each pixel includes an organic electroluminescence material. The lenses are arranged in a staggered pattern.

    摘要翻译： 有机电致发光显示装置包括多个像素和布置在其上的透镜阵列。 每个像素包括设置有透镜的发光区域和没有透镜而设置的发光区域。 每个像素的发光区域包括有机电致发光材料。 透镜以交错图案排列。