公开(公告)号：US07340552B2

公开(公告)日：2008-03-04

申请号：US11642511

申请日：2006-12-21

Applicant: Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

Inventor： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC: G06F13/14 ,  G06F13/36

CPC classification number: G06F13/4027 ,  G06F13/36

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract translation: 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US20070058777A1

公开(公告)日：2007-03-15

申请号：US10557713

申请日：2004-10-29

Applicant: Nobukazu Kondo

Inventor： Nobukazu Kondo

IPC: G01N23/04

CPC classification number: G01N23/04

Abstract: A hybrid type foreign matter detecting apparatus (1) includes magnet boosters (5), an X-ray detector (7), and sensor coils (8). When metallic foreign matter mixed in an object (6) under inspection transferred by a belt conveyor (4) passes through the magnet boosters (5), the magnetic properties of the foreign matter are enhanced so that the foreign matter is easy to detect with the sensor coils (8). X-rays generated from the X-ray detector (7) are focused in a region where the sensitivity of the sensor coils (8) is the lowest, whereby metallic foreign matter mixed in either of the surface and center portions of inspection objects can be detected satisfactorily.

Abstract translation: 混合型异物检测装置（1）包括磁体增强器（5），X射线检测器（7）和传感器线圈（8）。 当通过带式输送机（4）转印的被检查物体（6）中混合的金属异物通过磁体助力器（5）时，异物的磁特性得到提高，使得异物容易被检测 传感器线圈（8）。 从X射线检测器（7）产生的X射线聚焦在传感器线圈（8）的灵敏度最低的区域，由此在检查对象的表面和中心部分中混合的金属杂质可以是 检测到令人满意。

公开(公告)号：US06330629B1

公开(公告)日：2001-12-11

申请号：US09053069

申请日：1998-04-01

Applicant: Nobukazu Kondo ,  Setsuko Kojima ,  Tomohisa Kohiyama ,  Shigeto Oeda

Inventor： Nobukazu Kondo ,  Setsuko Kojima ,  Tomohisa Kohiyama ,  Shigeto Oeda

IPC: G06F1300

CPC classification number: G06F13/4059 ,  G06F13/4027

Abstract: An information processing system is configured such that which when an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, a sufficient processing performance is realized with the conventional CPU and bus capabilities. The information processing system includes a bus adaptor or bus converter for connecting a CPU bus and a system bus. The bus converter includes an operation processing unit (ALU) capable of performing a portion of an operating function performed by the conventional CPU or a portion of an operating function performed by an image processing board connected to the system bus, whereby the bus converter takes over a portion of a processing to be performed by the CPU or I/O module. Thereby, an overhead time for data transfer through the buses is reduced so that the total performance of the system is improved. Also, since a processing unqualified for the CPU, for example, a bit operation can be performed by a dedicated hardware, the information processing performance is improved.

Abstract translation: 信息处理系统被配置为使得当通过诸如个人计算机之类的信息处理器执行处理多媒体，特别是移动图像的应用时，利用传统的CPU和总线能力来实现足够的处理性能。 信息处理系统包括用于连接CPU总线和系统总线的总线适配器或总线转换器。 总线转换器包括能够执行由常规CPU执行的操作功能的一部分的操作处理单元或由连接到系统总线的图像处理板执行的操作功能的一部分，由此总线转换器接管 由CPU或I / O模块执行的处理的一部分。 因此，减少了通过总线的数据传输的开销时间，从而提高了系统的总体性能。 此外，由于对CPU不合格的处理，例如，可以通过专用硬件执行位操作，所以提高了信息处理性能。

公开(公告)号：US6047345A

公开(公告)日：2000-04-04

申请号：US78713

申请日：1998-05-14

Applicant: Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

Inventor： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/12 ,  G06F13/364 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/364

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

公开(公告)号：US6021455A

公开(公告)日：2000-02-01

申请号：US708324

申请日：1996-09-05

Applicant: Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

Inventor： Nobukazu Kondo ,  Koichi Okazawa ,  Yukihiro Seki ,  Ryuichi Hattori ,  Masaya Umemura ,  Shigemi Adachi ,  Kouichi Nakai ,  Takashi Moriyama

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/00

CPC classification number: G06F13/364

Abstract: An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.

Abstract translation: 一种信息处理系统，包括第一总线，第二总线，连接到两个总线的多个模块，用于仲裁总线主机的总线访问请求的总线仲裁器，以及用于存储高达预定量的访问数据的存储装置， 当访问目的地信息指示所述模块是访问目的地时，模块之一。 每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断总线主机之一发出总线访问请求时，总线仲裁器是指预定量的访问目的地信息是否完全存储在存储器中 意味着，并决定是否给总线访问总线主控。

公开(公告)号：US5881255A

公开(公告)日：1999-03-09

申请号：US847974

申请日：1997-04-21

Applicant: Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

Inventor： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40 ,  G06F12/00

CPC classification number: G06F13/4027 ,  G06F13/36

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US5671371A

公开(公告)日：1997-09-23

申请号：US544727

申请日：1995-10-18

Applicant: Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

Inventor： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC: G06F13/36 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/368 ,  G06F13/40 ,  G06I13/00

CPC classification number: G06F13/4027 ,  G06F13/36

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract translation: 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06665807B1

公开(公告)日：2003-12-16

申请号：US09389228

申请日：1999-09-03

Applicant: Nobukazu Kondo ,  Koki Noguchi ,  Ikuya Kawasaki

Inventor： Nobukazu Kondo ,  Koki Noguchi ,  Ikuya Kawasaki

IPC: G06F112

CPC classification number: G06F13/4059

Abstract: A circuit includes a transmission function of transmitting data together with a source clock synchronized to the data to another module, a reception circuit for receiving the data outputted by the module and a source clock synchronized to the data, and a synchronization circuit for connecting the circuit having a transmission function to the reception circuit are formed on a single-chip integrated circuit. Even if the module connected to the bus is changed, i.e., even if the operation clock frequency of the module of the other party is changed, other modules can be used as they are without making any change. The cost needed at the time of system construction can thus be reduced. Furthermore, as for the aspect of performance, only one synchronization circuit is needed. The increase of latency caused by synchronization can also be suppressed to the minimum.

Abstract translation: 电路包括将与数据同步的源时钟与数据一起发送的另一模块的发送功能，用于接收模块输出的数据的接收电路和与数据同步的源时钟，以及用于连接电路的同步电路 在单芯片集成电路上形成对接收电路具有传输功能。 即使连接到总线的模块被改变，即使对方的模块的操作时钟频率改变，也可以使用其他模块，而不进行任何改变。 因此可以减少系统建造时所需的成本。 此外，对于性能方面，仅需要一个同步电路。 由同步引起的延迟的增加也可以抑制到最小。

公开(公告)号：US06519667B2

公开(公告)日：2003-02-11

申请号：US09991925

申请日：2001-11-26

Applicant: Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

Inventor： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC: G06F1300

CPC classification number: G06F13/4027 ,  G06F13/36

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US6094521A

公开(公告)日：2000-07-25

申请号：US260498

申请日：1999-03-02

Applicant: Masataka Okayama ,  Tomohisa Kohiyama ,  Nobukazu Kondo ,  Kazutoshi Katoh ,  Kazuaki Tanaka ,  Yoshihiro Harada

Inventor： Masataka Okayama ,  Tomohisa Kohiyama ,  Nobukazu Kondo ,  Kazutoshi Katoh ,  Kazuaki Tanaka ,  Yoshihiro Harada

IPC: G06T9/00 ,  G11B27/10 ,  G11B27/11 ,  G11B27/28 ,  G11B27/32 ,  G11B27/34 ,  H04N5/77 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/804 ,  H04N5/91 ,  H04N5/76

CPC classification number: H04N5/772 ,  G06T9/007 ,  G11B27/105 ,  G11B27/11 ,  G11B27/28 ,  G11B27/329 ,  H04N9/8045 ,  G11B2220/20 ,  G11B27/34 ,  H04N5/77 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/8042

Abstract: An object is to provide a video recording/playing apparatus for facilitating recording/playing of motion pictures. The configuration is provided with, at least, a video input device for inputting analog motion pictures (video), a video capture device for digitizing the motion pictures inputted through the video input device and recording the digitized motion pictures and, at the same time, for converting the motion pictures inputted through the video input device into compressed motion pictures capable of being played in a high compression ratio and in a high picture quality and recording the compressed motion pictures, an information extracting device for extracting arbitrary information from the non-compressed motion pictures captured by the video capture device, a correspondence information generating device for associating the information extracted by the information extracting device with the compressed motion pictures captured by the video capture device, an input device for designating a result of the correspondence, and a compressed video playing device for playing the compressed motion pictures.

Abstract translation: 目的在于提供一种便于记录/播放动态影像的视频记录/播放装置。 该配置至少提供有用于输入模拟运动图像（视频）的视频输入装置，用于数字化通过视频输入装置输入的运动图像并记录数字化运动图像的视频捕获装置，并且同时， 用于将通过视频输入装置输入的运动图像转换为能够以高压缩比和高图像质量播放的压缩运动图像，并记录压缩的运动图像;信息提取装置，用于从非压缩 由视频捕捉装置拍摄的动态图像，将信息提取装置提取的信息与由视频捕获装置拍摄的压缩运动图像相关联的对应信息生成装置，用于指定对应结果的输入装置，以及压缩 用于播放压缩动画图片的视频播放设备 tures。