发明授权
- 专利标题: Low voltage CMOS circuit for on/off chip drive at high voltage
- 专利标题(中): 低压CMOS电路用于高电压开/关芯片驱动
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申请号: US4565申请日: 1998-01-08
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公开(公告)号: US6031394A公开(公告)日: 2000-02-29
- 发明人: Hayden C. Cranford, Jr. , Stacy J. Garvin , Geoffrey B. Stephens
- 申请人: Hayden C. Cranford, Jr. , Stacy J. Garvin , Geoffrey B. Stephens
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 主分类号: H03K3/356
- IPC分类号: H03K3/356 ; H03K17/10 ; H03K19/0175 ; H03K19/00 ; H03K19/003 ; H03K19/094
摘要:
A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.
公开/授权文献
- US4775181A Rear body structure of automobile 公开/授权日:1988-10-04
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