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公开(公告)号：US6031394A
公开(公告)日：2000-02-29
申请号：US4565
申请日：1998-01-08
IPC分类号： H03K3/356 , H03K17/10 , H03K19/0175 , H03K19/00 , H03K19/003 , H03K19/094
CPC分类号： H03K3/356147 , H03K17/102
摘要： A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.
摘要翻译： 低电压CMOS电路和方法提供满足多电压芯片驱动器多模式要求的输出电流能力，同时保护CMOS器件免受各种故障机制的影响。 电路和方法利用两个电源轨之间的中间电压和分压技术，将电压限制在任何所选技术中的CMOS器件的漏极到源极，栅极到漏极和栅极到源极的可接受的极限。 该电路包括第一和第二CMOS共源共栅链，其连接在例如5伏的高压电源轨和参考电位电源轨之间。 地面。 每个CMOS共源共栅链包括与第一和第二n型MOS器件串联的第一和第二p型MOS器件。 输入电路耦合到第一CMOS共源共栅链的中点的节点。 通常3.3伏的偏置电压连接到第一和CMOS共源共栅链中的NMOS器件。 第二偏置电压耦合到第一和第二CMOS共源共栅链中的PMOS器件。 从第二CMOS共源共栅链提供输出到第三CMOS共源共栅链，目的是提供足够的上拉能力，以在不超过任何MOS器件的击穿机制的情况下驱动包括高参考电位和参考电位之间的第四CMOS共源共栅链的输出电路 CMOS共源共栅链。
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2.发明授权Overshoot reduction in VCO calibration for serial link phase lock loop (PLL) 失效用于串行链路锁相环（PLL）的VCO校准过程减少公开(公告)号：US07539473B2
公开(公告)日：2009-05-26
申请号：US11411662
申请日：2006-04-26
IPC分类号： H04B1/18
CPC分类号： H03L7/18 , H03L7/0891
摘要： A circuit design, method, and system for tracking VCO calibration without requiring an over-designed divider as in conventional implementation. A filter reset component is added to the inputs of the VCO. A process step is added to the calibration mechanism/process that shorts the filter nodes and thus centers the frequency of the VCO before stepping from one frequency band to the next.
摘要翻译： 用于跟踪VCO校准的电路设计，方法和系统，而不需要如常规实现中的过度设计的分频器。 滤波器复位分量被添加到VCO的输入端。 在校准机构/过程中添加了一个处理步骤，该校准机构/过程使滤波器节点短路，并因此在从一个频带到下一个频带之前将VCO的频率居中。
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公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.
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公开(公告)号：US4638464A
公开(公告)日：1987-01-20
申请号：US551450
申请日：1983-11-14
IPC分类号： H01L27/10 , G11C5/00 , G11C5/14 , G11C11/407 , G11C14/00 , G11C16/06 , G11C17/00 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , H02M3/07 , G11C11/24
摘要： A voltage generating system provides a plurality of different voltages for powering a dynamic nonvolatile random access memory (NVRAM) chip. The voltage generating system includes a pair of charge pumps. Each charge pump is coupled to a controller that senses the voltage level at the output of the charge pump and generates an enabling signal when said voltage is at a predetermined value. The signal activates a power down circuit which adjusts the charge pump output to a desired voltage level. A programmable oscillator provides the clocking signals for the controller. The charge pumps and programmable oscillators are periodically deactivated. As a result, the overall power consumption of the chip is reduced.
摘要翻译： 电压产生系统提供多个不同的电压来为动态非易失性随机存取存储器（NVRAM）芯片供电。 电压发生系统包括一对电荷泵。 每个电荷泵耦合到控制器，该控制器感测电荷泵的输出端的电压电平，并且当所述电压处于预定值时产生使能信号。 该信号激活一个将电荷泵输出调节到所需电压电平的掉电电路。 可编程振荡器为控制器提供时钟信号。 定时停用电荷泵和可编程振荡器。 结果，芯片的总功耗降低。
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5.发明授权
公开(公告)号：US4536720A
公开(公告)日：1985-08-20
申请号：US551451
申请日：1983-11-14
IPC分类号： H01L27/10 , G11C11/407 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L29/788 , H01L29/792 , H03K3/03 , H03K3/354 , H03K3/70
CPC分类号： H03K3/354 , H03K3/0315 , H03K3/70
摘要： A programmable oscillator is provided for use on an integrated circuit chip. The oscillator includes a plurality of inverter delay stages connected in tandem between an input and an output node. A single FET device couples a node common to all of the inverter delay stages to a ground potential. Another FET device controls the input node. When a logic enabling signal is appropriately applied to the FET devices, the oscillator is controlled so that internal nodes of the oscillator float high when it is off and no energy is dissipated. In addition, the amount of delays between the delay stages and the input stage of the load is such that the load supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load.
摘要翻译： 提供了一种用于集成电路芯片的可编程振荡器。 该振荡器包括串联连接在输入和输出节点之间的多个反相器延迟级。 单个FET器件将所有反相器延迟级公共的节点耦合到地电位。 另一个FET器件控制输入节点。 当逻辑使能信号被适当地施加到FET器件时，振荡器被控制，使得振荡器的内部节点在关闭时浮起，并且没有能量消耗。 此外，延迟级与负载的输入级之间的延迟量使得负载提供较大的延迟比。 这确保振荡器的振荡频率跟踪负载的切换速度。
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公开(公告)号：US07268613B2
公开(公告)日：2007-09-11
申请号：US11263008
申请日：2005-10-31
IPC分类号： G05F3/02
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.
摘要翻译： 一种具有基于晶体管的开关拓扑的电路器件，其基本上消除了器件闭锁的可能性。 串联的低电压阈值（LVT）N沟道晶体管和上拉电阻跨越开关（P沟道）晶体管耦合，以便为开关晶体管提供一体的主体连接，开关晶体管连接 开关晶体管连接到LVT晶体管的上拉电阻和源极端子之间的一个节点。 LVT晶体管的栅极和漏极端子连接到开关晶体管的输出端子。 电阻器的另一端连接到开关晶体管的电源侧端子。 在特定配置中添加这些组件允许开关晶体管的主体连接自动切换到最高电位扩散节点。
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公开(公告)号：US07279950B2
公开(公告)日：2007-10-09
申请号：US11235758
申请日：2005-09-27
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.
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8.发明授权Circuit and method for reducing jitter in a PLL of high speed serial links 失效用于降低高速串行链路PLL的抖动的电路和方法公开(公告)号：US07042277B2
公开(公告)日：2006-05-09
申请号：US10685022
申请日：2003-10-14
IPC分类号： G01F1/10
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译： 降低高速串行链路的PLL中的抖动的方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调整。 调节器控制电路进行检查和控制。
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9.发明授权On chip multiple voltage generation using a charge pump and plural feedback sense circuits 失效使用电荷泵和多个反馈感测电路进行片上多电压生成
公开(公告)号：US4752699A
公开(公告)日：1988-06-21
申请号：US943466
申请日：1986-12-19
IPC分类号： H01L21/8247 , G11C5/14 , G11C16/06 , G11C16/30 , G11C17/00 , H01L21/822 , H01L27/04 , H01L29/788 , H01L29/792 , H02M3/00 , H02M3/07 , H03K5/00 , G05F1/571
摘要： A level selectable FET voltage generation system is described. The system includes a single charge pump controlled by multiple feedback paths and a powerdown circuit. Each feedback path contains a capacitor divider network, a sense amplifier with a compensating voltage reference and a timer which periodically resets the capacitor divider network to insure sensing accuracy. The powerdown circuit and a selected feedback path provides a desired voltage level at the output of the charge pump.
摘要翻译： 描述了电平可选FET电压产生系统。 该系统包括由多个反馈路径控制的单个电荷泵和断电电路。 每个反馈路径包含电容分压网络，具有补偿电压基准的读出放大器和周期性地复位电容分压器网络以确保感测精度的定时器。 断电电路和所选择的反馈路径在电荷泵的输出处提供期望的电压电平。
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公开(公告)号：US07486127B2
公开(公告)日：2009-02-03
申请号：US11835298
申请日：2007-08-07
IPC分类号： H03K3/01
CPC分类号： H03K17/161 , H03K2217/0018
摘要： A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.
摘要翻译： 一种具有基于晶体管的开关拓扑的电路器件，其基本上消除了器件闭锁的可能性。 串联的低电压阈值（LVT）N沟道晶体管和上拉电阻跨越开关（P沟道）晶体管耦合，以便为开关晶体管提供一体的主体连接，开关晶体管连接 开关晶体管连接到LVT晶体管的上拉电阻和源极端子之间的一个节点。 LVT晶体管的栅极和漏极端子连接到开关晶体管的输出端子。 电阻器的另一端连接到开关晶体管的电源侧端子。 在特定配置中添加这些组件允许开关晶体管的主体连接自动切换到最高电位扩散节点。
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