- 专利标题: Voltage level converter circuit improved in operation reliability
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申请号: US45568申请日: 1998-03-23
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公开(公告)号: US6049243A公开(公告)日: 2000-04-11
- 发明人: Masaaki Mihara , Yasuhiko Taito
- 申请人: Masaaki Mihara , Yasuhiko Taito
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX9-251860 19970917
- 主分类号: G11C11/34
- IPC分类号: G11C11/34 ; G05F1/56 ; G05F3/24 ; G11C5/14 ; G11C16/06 ; G11C16/12 ; H03K19/0185
摘要:
A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
公开/授权文献
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