A system for use in a computer, the system comprises a memory device and a controller or master to generate a request to provide data. The memory device includes at least one section of memory, having a plurality of memory cells, and a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before the memory device outputs data onto the bus in response to the request to provide data. The memory device may further include a plurality of output drivers and a delay lock loop circuitry wherein the delay lock loop circuitry generates a first internal clock signal using the first external clock signal. The plurality of output drivers, in response to the first internal clock signal, output data onto the bus. The plurality of output drivers output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal. The delay lock loop circuitry may also generate the first internal clock signal using the first external clock signal and a second external clock signal.