Invention Grant
- Patent Title: Synchronization of weakly ordered write combining operations using a fencing mechanism
- Patent Title (中): 使用栅栏机制同步弱序写入组合操作
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Application No.: US53377Application Date: 1998-03-31
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Publication No.: US6073210APublication Date: 2000-06-06
- Inventor: Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
- Applicant: Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
- Applicant Address: CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: CA Santa Clara
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F13/16 ; G06F13/14 ; G06F12/00
Abstract:
The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
Public/Granted literature
- US4766646A Poultry processing Public/Granted day:1988-08-30
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