-
公开(公告)号：US20150186232A1
公开(公告)日：2015-07-02
申请号：US14141099
申请日：2013-12-26
Applicant: Jeremy Conner , Sabar Souag , Karunakara Kotary , Victor Ruybalid , Noel Eck , Ramana Rachakonda , Sankaran Menon , Lance Hacking
Inventor： Jeremy Conner , Sabar Souag , Karunakara Kotary , Victor Ruybalid , Noel Eck , Ramana Rachakonda , Sankaran Menon , Lance Hacking
CPC classification number: G06F11/2268 , G06F11/26 , G06F11/3024 , G06F11/3082 , G06F11/3086 , G06F11/3476 , G06F11/3656 , G06F2201/835 , G06F2201/865
Abstract: Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The techniques may include recording the debug data at a storage element, wherein the storage element is disposed in a non-core portion of the circuit interconnect accessible to the agents.
Abstract translation: 这里描述了调试计算系统的技术。 这些技术可以包括在计算系统中的代理处生成调试数据。 这些技术可以包括将调试数据记录在存储元件处，其中存储元件设置在代理可访问的电路互连的非核心部分中。
-
公开(公告)号：US08050177B2
公开(公告)日：2011-11-01
申请号：US12060157
申请日：2008-03-31
Applicant: Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
Inventor： Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/3243 , G06F13/42 , G06F15/17306 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable.
Abstract translation: 公开了一种互连带宽调节器。 基于在预定的节气门窗口内是否发生最大数量的交易，互连带宽调节器关闭互连。 最大交易数量和油门窗口均可调。
-
3.发明申请公开(公告)号：US20050273635A1
公开(公告)日：2005-12-08
申请号：US10871638
申请日：2004-06-17
Applicant: Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Lance Hacking
Inventor： Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Lance Hacking
CPC classification number: G06F1/26 , G06F1/3203 , G06F1/3246 , G06F1/3287 , Y02D10/171 , Y10T307/438
Abstract: Methods and apparatuses for coordination of power state management in and electronic system.
Abstract translation: 电力系统管理与电力系统协调的方法与装置。
-
4.发明授权
公开(公告)号：US6073210A
公开(公告)日：2000-06-06
申请号：US53377
申请日：1998-03-31
Applicant: Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
Inventor： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
CPC classification number: G06F13/1631 , G06F12/0802
Abstract: The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
Abstract translation: 本发明公开了一种用于使弱顺序的写入组合操作同步的方法和装置。 存储器控制器具有用于服务存储器访问的缓冲器。 存储栏指令被发送到存储器控制器。 如果缓冲区至少包含由存储栏指令之前的弱顺序写入组合操作中的至少一个写入的数据，则存储栅栏指令被阻止，直到包含数据的缓冲区中的块被全局观察到。 如果在存储栏指令之前缓冲器不包含写入组合操作中的至少一个写入的任何数据，则存储器控制器接受存储栅栏指令。
-
公开(公告)号：US20050273633A1
公开(公告)日：2005-12-08
申请号：US10859892
申请日：2004-06-02
Applicant: Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Bernard Lint , Lance Hacking
Inventor： Jeffrey Wilcox , Shivnandan Kaushik , Stephen Gunther , Devadatta Bodas , Siva Ramakrishnan , David Poisner , Bernard Lint , Lance Hacking
CPC classification number: G06F1/3203
Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.
Abstract translation: 管理电力的系统和方法提供接收待决功率状态转换的通知并使用协调硬件来确定主设备中的电力状态转换是否被一组辅助设备所允许。 在一个实施例中，主设备与该组次级设备共享资源。
-
Patent Agency Ranking
公开(公告)号：US20140149999A1
公开(公告)日：2014-05-29
申请号：US14167688
申请日：2014-01-29
Applicant: Lance Hacking
Inventor： Lance Hacking
IPC: G06F9/54
CPC classification number: G06F9/542 , G06F11/30 , G06F11/3466 , G06F2201/86 , G06F2201/88 , G06F2201/885
Abstract: A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic.
Abstract translation: 监控计算机系统或集成电路中的事件的技术。 在一个实施例中，可以选择软件可访问事件监视存储和硬件特定的监视逻辑，并且可以通过访问计数器来监视其对应的输出，以计数与软件可访问的存储和硬件特定的监视逻辑中的每一个对应的事件。
-
公开(公告)号：US08312309B2
公开(公告)日：2012-11-13
申请号：US12042985
申请日：2008-03-05
Applicant: Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
Inventor： Eric L. Hendrickson , Sanjoy Mondal , Larry Thatcher , William Hodges , Lance Hacking , Sankaran Menon
CPC classification number: G06F1/12
Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.
Abstract translation: 一种用于促进计算机系统或集成电路内的多个时钟域之间的确定性的技术。在一个实施例中，一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。
-
公开(公告)号：US20120054387A1
公开(公告)日：2012-03-01
申请号：US13241738
申请日：2011-09-23
Applicant: Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
Inventor： Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
IPC: G06F13/42
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/3243 , G06F13/42 , G06F15/17306 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler.
Abstract translation: 公开了一种互连带宽调节器。 基于在预定的节气门窗口内是否发生了最大数量的交易，互连带宽调节器关闭互连。 最大交易数量和油门窗口均可调。 使用互连带宽调节器可以调整性能，散热和平均功耗等特性。
-
公开(公告)号：US07707350B2
公开(公告)日：2010-04-27
申请号：US12057796
申请日：2008-03-28
Applicant: Michael E. Altenburg , Binta M. Patel , Lance Hacking , David K. Dean
Inventor： Michael E. Altenburg , Binta M. Patel , Lance Hacking , David K. Dean
IPC: G06F13/36
CPC classification number: G06F13/4013
Abstract: A front side bus swizzle mechanism modifies the front side (address and data) bus on a chip so that, when the chip is positioned on one side of a printed circuit board, connection to a second chip located on the opposite side of the printed circuit board is simplified. The simplified connection may result in less complexity and minimize the consumption of additional printed circuit board real estate.
Abstract translation: 前端总线旋转机构将芯片上的正面（地址和数据）总线修改为使得当芯片位于印刷电路板的一侧时，连接到位于印刷电路相对侧上的第二芯片 板简化了。 简化的连接可能导致更少的复杂性和最小化附加印刷电路板不动产的消耗。
-
公开(公告)号：US20090248927A1
公开(公告)日：2009-10-01
申请号：US12060157
申请日：2008-03-31
Applicant: Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
Inventor： Lance Hacking , Ramana Rachakonda , Belliappa Kuttanna , Rajesh Patel
IPC: G06F13/42
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/3243 , G06F13/42 , G06F15/17306 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable.
Abstract translation: 公开了一种互连带宽调节器。 基于在预定的节气门窗口内是否发生最大数量的交易，互连带宽调节器关闭互连。 最大交易数量和油门窗口均可调。
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.011 seconds)
