发明授权
- 专利标题: Bandgap reference voltage generating circuit
- 专利标题(中): 带隙基准电压发生电路
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申请号: US325733申请日: 1999-06-04
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公开(公告)号: US6084391A公开(公告)日: 2000-07-04
- 发明人: Tadashi Onodera
- 申请人: Tadashi Onodera
- 申请人地址: JPX Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX10-157770 19980605
- 主分类号: G05F3/02
- IPC分类号: G05F3/02 ; G05F3/24 ; G05F3/26 ; G05F3/16
摘要:
In a bandgap reference voltage generating circuit having first, second and third unitary circuits connected in parallel between a power supply voltage and a ground, there is added a fourth unitary circuit including an n-channel FET turned on in response to a bias voltage applied to a gate of the n-channel FET. The second unitary circuit is connected to the fourth unitary circuit through a capacitor having one end connected to a drain of the n-channel FET. When the bias voltage is applied to turn on the n-channel FET of the fourth unitary circuit, since the potential of the one end of the capacitor is dropped, a gate potential of n-channel FETs included in the first and second unitary circuits and operating in a weak inversion condition quickly becomes definite, so that a reference voltage can be generated quickly.
公开/授权文献
- US5475443A On-screen display circuit of imaging system 公开/授权日:1995-12-12
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