公开(公告)号：US07515496B2

公开(公告)日：2009-04-07

申请号：US11984352

申请日：2007-11-16

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

摘要翻译： 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

公开(公告)号：US07432753B2

公开(公告)日：2008-10-07

申请号：US11907863

申请日：2007-10-18

申请人： Tadashi Onodera

发明人： Tadashi Onodera

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/15066

摘要： A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

摘要翻译： 延迟电路包括：N级电路，具有级联连接的第N电路的第一电路，输入信号被输入到第一电路和延迟了（k-1）级的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间 由公共延迟电路通过第i电路延迟的信号，公共延迟电路连接到信号路径，而在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共 延迟电路产生N次。

公开(公告)号：US07307909B2

公开(公告)日：2007-12-11

申请号：US11297646

申请日：2005-12-09

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

摘要翻译： 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

公开(公告)号：US07292086B2

公开(公告)日：2007-11-06

申请号：US11318526

申请日：2005-12-28

申请人： Tadashi Onodera

发明人： Tadashi Onodera

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/15066

摘要： A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

摘要翻译： 延迟电路包括：N级电路，其具有第一级联到级联的第N级电路，输入信号被输入到第一电路和延迟了（k-1）阶段的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间 由公共延迟电路通过第i个电路延迟的信号，公共延迟电路连接到信号路径，在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共 延迟电路产生N次。

公开(公告)号：US20060145667A1

公开(公告)日：2006-07-06

申请号：US11297646

申请日：2005-12-09

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： H02J7/04

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

公开(公告)号：US07978543B2

公开(公告)日：2011-07-12

申请号：US12488920

申请日：2009-06-22

申请人： Hideo Inaba ,  Tadashi Onodera

发明人： Hideo Inaba ,  Tadashi Onodera

IPC分类号： G11C7/10

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

摘要翻译： 半导体器件包括：第一和第二输入/输出端子; 连接到第一输入/输出端的第一输入/输出线; 连接到第二输入/输出端子的第二输入/输出线; 以及连接第一输入/输出线和第二输入/输出线的第一旁路路径。 当处于正常操作模式时，第一个旁路路由被设置为非导通状态。 当处于测试模式时，将第一旁路路径设置为导通状态，使得输入到第一输入/输出端的第一数据作为第一数据输出到第二输入/输出线， 并且使得输入到所述第一输入/输出端的第二数据作为所述第一输入/输出线的第二输入数据被输出，以对应于所述第二输入/输出端中的所述时钟信号的转变 方向。

公开(公告)号：US20080048749A1

公开(公告)日：2008-02-28

申请号：US11907863

申请日：2007-10-18

申请人： Tadashi ONODERA

发明人： Tadashi ONODERA

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/15066

摘要： A delay circuit comprises: N-stage circuits having a first circuit to an N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k−1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

公开(公告)号：US20060139079A1

公开(公告)日：2006-06-29

申请号：US11318526

申请日：2005-12-28

申请人： Tadashi Onodera

发明人： Tadashi Onodera

IPC分类号： H03H11/26

CPC分类号： H03K5/1506 ,  H03K5/15066

摘要： A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2≦k≦N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1≦i≦N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

摘要翻译： 延迟电路包括：N级电路，其具有第一级联到级联的第N级电路，输入信号被输入到第一电路和延迟了（k-1）阶段的传输信号（其中2 < = k <= N）电路输入到第k个电路进行顺序传输; 用于延迟每个级的传输信号的公共延迟电路; 以及路径控制装置，用于控制第i（1≤i≤N）个电路的路径，使得在从输入到第i个电路的信号的边沿定时到传输的边缘定时的预定时段期间 由公共延迟电路通过第i电路延迟的信号，公共延迟电路连接到信号路径，而在另一周期期间，公共延迟电路与信号路径断开，其中延迟信号通过公共 延迟电路产生N次。

公开(公告)号：US20090316495A1

公开(公告)日：2009-12-24

申请号：US12488920

申请日：2009-06-22

申请人： Hideo INABA ,  Tadashi ONODERA

发明人： Hideo INABA ,  Tadashi ONODERA

IPC分类号： G11C7/10 ,  G11C29/00 ,  G11C8/18

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.

摘要翻译： 半导体器件包括：第一和第二输入/输出端子; 连接到第一输入/输出端的第一输入/输出线; 连接到第二输入/输出端子的第二输入/输出线; 以及连接第一输入/输出线和第二输入/输出线的第一旁路路径。 当处于正常操作模式时，第一个旁路路由被设置为非导通状态。 当处于测试模式时，将第一旁路路径设置为导通状态，使得输入到第一输入/输出端的第一数据作为第一数据输出到第二输入/输出线， 并且使得输入到所述第一输入/输出端的第二数据作为所述第一输入/输出线的第二输入数据被输出，以对应于所述第二输入/输出端中的所述时钟信号的转变 方向。

公开(公告)号：US20080074940A1

公开(公告)日：2008-03-27

申请号：US11984352

申请日：2007-11-16

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： G11C7/04

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

摘要翻译： 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。