发明授权
- 专利标题: Method for increasing power supply bypassing while decreasing chip layer density variations
- 专利标题(中): 增加电源旁路同时降低芯片层密度变化的方法
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申请号: US204021申请日: 1998-12-01
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公开(公告)号: US6118169A公开(公告)日: 2000-09-12
- 发明人: Paul D Nuber , Dan Stotz , M. Jason Welch , Stephen E. Clarke , Guy H. Humphrey , C. Stephen Dondale
- 申请人: Paul D Nuber , Dan Stotz , M. Jason Welch , Stephen E. Clarke , Guy H. Humphrey , C. Stephen Dondale
- 申请人地址: CA Palo Alto
- 专利权人: Agilent Technologies
- 当前专利权人: Agilent Technologies
- 当前专利权人地址: CA Palo Alto
- 主分类号: H01L27/04
- IPC分类号: H01L27/04 ; H01L21/77 ; H01L21/822 ; H01L27/118
摘要:
A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.
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