公开(公告)号：US06188260B1

公开(公告)日：2001-02-13

申请号：US09235189

申请日：1999-01-22

申请人： Dan Stotz ,  Raymond W Rosenberry ,  Kent R Townley ,  Gayvin E Stong

发明人： Dan Stotz ,  Raymond W Rosenberry ,  Kent R Townley ,  Gayvin E Stong

IPC分类号： H03K3289

CPC分类号： H03K3/0372

摘要： A master-slave flip-flop and method is provided for use with critical path circuits, for example, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input inverter coupled to the pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter. The output of the driving inverter is coupled to the slave stage which includes a second pass gate through which the output of the driving inverter is applied to the master-slave flip-flop output. The above architecture results in a fast setup time and a fast clock-to-Q time without the problems associated with kickback. Also, the output of the master-slave flip-flop is tristatable.

摘要翻译： 主 - 从触发器和方法被提供用于关键路径电路，例如驱动集成电路上的输出焊盘。 简要描述，在架构中，主从触发器包括主站和从站。 主级包括通路，耦合到通路的输入反相器，耦合在输入反相器两端的反馈反相器和耦合到输入反相器的输出的驱动反相器。 驱动逆变器的输出耦合到从动级，该副级包括第二级通过栅极，驱动逆变器的输出通过该第二通道施加到主从触发器输出端。 上述架构导致快速建立时间和快速的时钟到Q时间，而没有与回扣相关的问题。 此外，主从触发器的输出也是可调整的。

公开(公告)号：US6118169A

公开(公告)日：2000-09-12

申请号：US204021

申请日：1998-12-01

申请人： Paul D Nuber ,  Dan Stotz ,  M. Jason Welch ,  Stephen E. Clarke ,  Guy H. Humphrey ,  C. Stephen Dondale

发明人： Paul D Nuber ,  Dan Stotz ,  M. Jason Welch ,  Stephen E. Clarke ,  Guy H. Humphrey ,  C. Stephen Dondale

IPC分类号： H01L27/04 ,  H01L21/77 ,  H01L21/822 ,  H01L27/118

CPC分类号： H01L27/118

摘要： A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.

摘要翻译： 提出了一种用于增加集成电路的包括多个功能块的导电层之间的层密度均匀性的方法。 通过在功能块之间平铺多个电容器来实现均匀性的提高。 布置电容器阵列的配置和阵列中的电容器单元的数量，以便在整个导电层上提供导体与非导体密度的近似均匀性。 电容器阵列可以用于通过将构成电容器阵列的一个或多个电容器单元耦合在高功率轨道和低功率轨道之间来降低电源开关噪声。

公开(公告)号：US06181182B2

公开(公告)日：2001-01-30

申请号：US09272042

申请日：1999-03-18

申请人： Dan Stotz ,  Richard A. Krzyzkowski ,  Paul D. Nuber

发明人： Dan Stotz ,  Richard A. Krzyzkowski ,  Paul D. Nuber

IPC分类号： H03K500

CPC分类号： H03K19/018571 ,  G06F1/10 ,  H03K19/01721 ,  H03L7/0812

摘要： A high gain, low input capacitance clock buffer includes a plurality of transistors configured to supply an inverted representation of an input reference signal by alternatively switching to provide the output. While either of the transistors is operating to switch the input clock signal, the other transistor is in a stable state. Furthermore, by using n-type FET's, significant power reduction and space savings may be achieved.

摘要翻译： 高增益低输入电容时钟缓冲器包括被配置为通过交替切换来提供输入参考信号的反相表示以提供输出的多个晶体管。 当晶体管中的任一个都工作以切换输入时钟信号时，另一晶体管处于稳定状态。 此外，通过使用n型FET，可以实现显着的功率减少和空间节省。

公开(公告)号：US06300822B1

公开(公告)日：2001-10-09

申请号：US09104921

申请日：1998-06-25

申请人： Brian Cardanha ,  Dan Stotz ,  Kent R. Townley

发明人： Brian Cardanha ,  Dan Stotz ,  Kent R. Townley

IPC分类号： G05F110

CPC分类号： G05F1/467

摘要： The inventive mechanism provides a hysteresis margin to a comparator. The inventive mechanism generates two different voltage values, one high level and one low level, which forms the noise margin. The mechanism will select the proper level based on the output of the comparator. The comparator will then use the selected reference voltage, having either a slightly higher or lower level than a nominal reference value, as the reference voltage in its operations. The difference between each level and the nominal level is the added hysteresis noise margin. The inventive mechanism uses the higher voltage level when the output of the comparator is below the nominal reference voltage, and uses the lower voltage level when the output of the comparator is above the nominal reference voltage. Thus, a noise spike in the input signal would have to be larger than the margin provided by the mechanism, before causing the comparator to react to the noise in the signal. Since the mechanism is separate from the comparator, different comparators do not have be designed and tested. The mechanism can be disabled by a shorting some of the nodes of the mechanism together during the metal layer step of the device fabrication.

摘要翻译： 本发明的机构向比较器提供滞后余量。 本发明机构产生形成噪声容限的两个不同的电压值，一个高电平和一个低电平。 该机制将根据比较器的输出选择适当的电平。 然后比较器将使用所选择的参考电压作为其运行中的参考电压，具有比标称参考值略高或更低的电平。 每个电平和额定电平之间的差值是增加的滞后噪声容限。 当比较器的输出低于额定参考电压时，本发明的机构使用较高的电压电平，并且当比较器的输出高于标称参考电压时使用较低的电压电平。 因此，在使比较器对信号中的噪声作出反应之前，输入信号中的噪声尖峰将必须大于由该机构提供的余量。 由于该机制与比较器分离，因此不需要对不同的比较器进行设计和测试。 可以通过在器件制造的金属层步骤期间将机构的一些节点一起短路来禁用该机制。