发明授权
US6133147A Process for selective metal deposition in holes of semiconductor device 失效
在半导体器件的孔中选择性金属沉积的工艺

Process for selective metal deposition in holes of semiconductor device
摘要:
A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.-12 to 10 torr for a controlled time period so that a blocking layer is formed only on the outer surface of the insulating layer, the blocking layer not extending over the inside walls of the hole, iv) selectively depositing a conductive metal in the hole using a chemical vapor deposition method to form the metallic interconnecting plug which extends from the surface of the semiconductor substrate or the metal underlayer to the level of the outer surface of the insulating layer, and v) removing the blocking layer from the surface of the insulating layer.
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