Process for selective metal deposition in holes of semiconductor device
    1.
    发明授权
    Process for selective metal deposition in holes of semiconductor device 失效
    在半导体器件的孔中选择性金属沉积的工艺

    公开(公告)号:US6133147A

    公开(公告)日:2000-10-17

    申请号:US139701

    申请日:1998-08-25

    CPC分类号: H01L21/76879

    摘要: A process for preparing a metallic interconnecting plug in a semiconductor device which comprises the steps of: i) forming an insulating layer on the surface of a semiconductor substrate or a metal underlayer of the semiconductor device, ii) forming a hole in the insulating layer to expose the surface of the semiconductor substrate or the metal underlayer, iii) exposing the surface of the insulating layer to the vapor of a blocking agent under a pressure ranging from 10.sup.-12 to 10 torr for a controlled time period so that a blocking layer is formed only on the outer surface of the insulating layer, the blocking layer not extending over the inside walls of the hole, iv) selectively depositing a conductive metal in the hole using a chemical vapor deposition method to form the metallic interconnecting plug which extends from the surface of the semiconductor substrate or the metal underlayer to the level of the outer surface of the insulating layer, and v) removing the blocking layer from the surface of the insulating layer.

    摘要翻译: 一种在半导体器件中制备金属互连插头的方法,包括以下步骤:i)在半导体器件的半导体衬底或金属底层的表面上形成绝缘层,ii)在绝缘层中形成孔, 暴露半导体衬底或金属底层的表面,iii)在10-12至10托的压力下将绝缘层的表面暴露于封闭剂的蒸气一段受控的时间段内,使得阻挡层为 仅形成在绝缘层的外表面上,阻挡层不延伸到孔的内壁上,iv)使用化学气相沉积法选择性地在孔中沉积导电金属,以形成金属互连插塞,其从 半导体衬底或金属底层的表面到绝缘层的外表面的水平面,以及v)从第二绝缘层去除阻挡层 e表面的绝缘层。

    Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique
    2.
    发明申请
    Method of fabricating silicon-doped metal oxide layer using atomic layer deposition technique 审中-公开
    使用原子层沉积技术制造掺杂硅的金属氧化物层的方法

    公开(公告)号:US20060257563A1

    公开(公告)日:2006-11-16

    申请号:US11329696

    申请日:2006-01-11

    IPC分类号: C23C16/00

    摘要: There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor. The sequence of operations of repeatedly performing the metal oxide layer formation cycle K times, followed by repeatedly performing the silicon-doped metal oxide layer formation cycle Q times, is performed one or more times until a silicon-doped metal oxide layer with a desired thickness is formed on the substrate. In addition, a method of fabricating a silicon-doped hafnium oxide (Si-doped HfO2) layer according to a similar invention method is also provided.

    摘要翻译: 提供了使用原子层沉积技术在半导体衬底上制造掺硅金属氧化物层的方法。 这些方法包括重复进行金属氧化物层形成循环K次的操作和重复进行掺硅金属氧化物层形成循环Q次的操作。 值K和Q中的至少一个是2以上的整数。 K和Q分别为1至约10的整数。 金属氧化物层形成循环包括将金属源气体供给到包含基板的反应器中,然后将氧化物气体注入到反应器中的步骤。 掺杂硅的金属氧化物层形成循环包括将含有硅的金属源气体供给到含有该基板的反应器中,然后将氧化物气体注入反应器。 重复执行金属氧化物层形成循环K次的操作顺序,随后重复进行掺杂硅的金属氧化物层形成循环Q次,执行一次或多次,直到具有所需厚度的掺硅金属氧化物层 形成在基板上。 此外,还提供了根据类似的发明方法制造掺杂硅的氧化铪(Si掺杂的HfO 2 N 2)层的方法。

    Yttrium-doped bismuth titanate thin film and preparation thereof
    3.
    发明授权
    Yttrium-doped bismuth titanate thin film and preparation thereof 失效
    掺钇钛酸铋薄膜及其制备方法

    公开(公告)号:US07250228B2

    公开(公告)日:2007-07-31

    申请号:US10672753

    申请日:2003-09-26

    IPC分类号: B32B9/00 C23C16/00

    摘要: A bismuth yttrium titanate (BYT) film having the composition of formula (I) has enhanced residual polarization and electric fatigue properties with excellent ferroelectric property, and therefore, it can be advantageously used in an electric or electronic device including a FRAM device: Bi4-xYxTi3O12  (I) wherein x is an integer of 0.1 to 2.

    摘要翻译: 具有式(I)组成的铋钛酸铋(BYT)膜具有优异的铁电性能的增强的残余极化和电疲劳特性,因此可有利地用于包括FRAM器件的电气或电子设备中。 in-line-formula description =“In-line Formulas”end =“lead”?> Bi x 4 x x Y 3 x 3 (I)<?in-line-formula description =“In-line Formulas”end =“tail”?>其中x为0.1至2的整数。

    Method for preparing low dielectric films
    4.
    发明授权
    Method for preparing low dielectric films 失效
    制备低介电膜的方法

    公开(公告)号:US07087271B2

    公开(公告)日:2006-08-08

    申请号:US10480770

    申请日:2002-06-28

    IPC分类号: H05H1/24

    摘要: A low dielectric constant hydrogenated silicon-oxycarbide (SiCO:H) film is prepared by bringing an organosilicon or organosilicate compound having at least one vinyl or ethynyl group, or a mixture of a saturated organosilicon or organosilicate compound and an unsaturated hydrocarbon into contact with a substrate in the presence of an O2-containing gas plasma.

    摘要翻译: 通过使具有至少一个乙烯基或乙炔基的有机硅或有机硅酸盐化合物或饱和有机硅或有机硅酸盐化合物和不饱和烃的混合物与一种低介电常数的氢化硅 - 碳氧化物(SiCO:H) 在含有O 2 N 2的气体等离子体存在下进行。