A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.