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发明授权
US6147531A Sampled delay locked loop insensitive to clock duty cycle 失效
采样延迟锁定环对时钟占空比不敏感

Sampled delay locked loop insensitive to clock duty cycle
摘要：
A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.
摘要（中）：

用于将数据信号写入驱动器的读/写盘驱动系统中的写通道包括一可变延迟电路，其具有多个用于校正非线性转换移位的可选抽头; 以及响应于用于控制可变电路的延迟的数据信号的延迟锁定环电路。

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