公开(公告)号：US5598364A

公开(公告)日：1997-01-28

申请号：US560002

申请日：1995-11-17

申请人： Kevin J. McCall ,  Janos Kovacs ,  Wyn Palmer

发明人： Kevin J. McCall ,  Janos Kovacs ,  Wyn Palmer

IPC分类号： G11B20/10 ,  G11B20/22 ,  H03K5/135 ,  H03L7/099 ,  G11C13/00

CPC分类号： H03L7/0805 ,  G11B20/10 ,  H03K5/135 ,  H03L7/0995

摘要： A write precompensation circuit includes a plurality of current-controlled delay buffers connected to form a delay line having selectable output taps. The precise delay of each delay buffer is controllable by a secondary control current derived from a master control current such that the precise delay is a precise percent of an oscillator period. The master control current is also used to control the period of a master write clock generated by a current-controlled ring oscillator of delay buffers. A write precompensation method includes steps of controlling current in delay buffers in a current-controlled ring oscillator used to generate a master write clock and current in delay buffers in a current-controlled delay line to maintain delays through delay buffers of the oscillator and the delay line in predetermined proportions to each other.

摘要翻译： 写入预补偿电路包括多个电流控制延迟缓冲器，连接形成具有可选输出抽头的延迟线。 每个延迟缓冲器的精确延迟可以通过从主控制电流导出的次级控制电流来控制，使得精确的延迟是振荡器周期的精确百分比。 主控制电流也用于控制由延迟缓冲器的电流控制环形振荡器产生的主写时钟的周期。 写预补偿方法包括以下步骤：控制用于在电流控制延迟线中产生主写时钟和延迟缓冲器中的电流的电流控制环形振荡器中的延迟缓冲器中的电流，以通过振荡器的延迟缓冲器和延迟来维持延迟 以预定比例相互排列。

公开(公告)号：US6147531A

公开(公告)日：2000-11-14

申请号：US112889

申请日：1998-07-09

申请人： Kevin J. McCall ,  Janos Kovacs

发明人： Kevin J. McCall ,  Janos Kovacs

IPC分类号： G11B20/10 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0891 ,  G11B20/10009 ,  H03L7/0812

摘要： A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

摘要翻译： 用于将数据信号写入驱动器的读/写盘驱动系统中的写通道包括一可变延迟电路，其具有多个用于校正非线性转换移位的可选抽头; 以及响应于用于控制可变电路的延迟的数据信号的延迟锁定环电路。

公开(公告)号：US6144981A

公开(公告)日：2000-11-07

申请号：US174944

申请日：1998-10-19

申请人： Janos Kovacs ,  Kevin J. McCall

发明人： Janos Kovacs ,  Kevin J. McCall

IPC分类号： H03H11/04 ,  G06G7/02

CPC分类号： H03H11/0444

摘要： A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

摘要翻译： 用于低通梯形滤波器的可编程脉冲微型系统包括滤波器输入电流源，用于向低通梯形滤波器提供要滤波的输入信号; 以及高频升压电流源，用于向第一电感器件前面的低通梯形滤波器注入高频负载电流，该高频负载电流是输入信号的缩放反向复制品，以在低通带的高频端提供增益 低通梯过滤器。

公开(公告)号：US07881309B2

公开(公告)日：2011-02-01

申请号：US10416036

申请日：2001-11-06

申请人： Jouni Pirhonen ,  Vesa Taivalantti ,  Krisztian Litkey ,  Mika Lindroos ,  Janos Kovacs ,  Esa Sarkama

发明人： Jouni Pirhonen ,  Vesa Taivalantti ,  Krisztian Litkey ,  Mika Lindroos ,  Janos Kovacs ,  Esa Sarkama

IPC分类号： H04L12/28

CPC分类号： H04W28/20 ,  H04L29/06027 ,  H04L65/103 ,  H04L65/104 ,  H04L65/1043 ,  H04L65/608 ,  H04L65/80 ,  H04W4/24 ,  H04W88/16

摘要： When a service is provided in a service stream between end devices controlling the service stream by using first protocol, there is also a need to control the service stream in the network via which the service stream is or is to be transmitted. The service stream is controlled in the network by utilizing first protocol messages which are separated (204) from other traffic transmitted in the network.

摘要翻译： 当通过使用第一协议在服务流中控制服务流的服务流中提供服务时，还需要控制网络中的服务流，通过该服务流来传送服务流。 通过利用与在网络中传输的其他流量分离（204）的第一协议消息，在网络中控制服务流。

公开(公告)号：US4576637A

公开(公告)日：1986-03-18

申请号：US651849

申请日：1984-09-18

申请人： Istvan Tamas ,  Szilard Riederauer ,  Janos Kovacs

发明人： Istvan Tamas ,  Szilard Riederauer ,  Janos Kovacs

IPC分类号： C22C33/04 ,  C21C5/52 ,  C22B1/24 ,  C22C33/00 ,  C22B4/00

CPC分类号： C22C33/003 ,  C21C5/5264 ,  C22B1/2406 ,  Y02P10/216

摘要： A process for the continuous preparation of silicon-base complex ferrous alloys from cheap raw materials by preparing a charge with a high electric resistance and reducing the same in an electric arc furnace. A charge is assembled which contains the total amount of carbon in a 0.82 to 0.99-fold quantity of that required to reduce all oxides of the charge to elements and achieving this carbon content by preparing pellets which, in addition to the binding material, contain(a) as oxide to be reduced in an amount of at least 50% by weight such oxides of only base-forming or only amphoteric or only acid-forming elements which form with each other compounds or eutectics melting above 1600.degree. C., and(b) a carbonaceous reducing agent and/or carbides in such an amount that the quantity of carbon is either 1.05 to 1.35 times higher than required to transform the oxides of the pellet to the carbides or 0.66 to 0.02-fold of the quantity required to reduce the oxides of the pellet to metallic elements, and assembling the charge(.alpha.) from pellets containing an excess of carbon and/or from lumpy carbides and(.beta.) from carbon-deficient pellets or from a lumpy oxide of a base-forming or amphoteric or acid-forming element and(.gamma.) from lumpy carbon carriers, and optionally(.delta.) from an iron additive, in the absence of boron trioxide.

摘要翻译： 一种通过在电弧炉中制备具有高电阻并在电弧炉中还原的方法从廉价原料连续制备硅基复合铁合金的方法。 组装电荷，其含有将元素中的所有电荷的所有氧化物还原并达到该碳含量所需的0.82至0.99倍的总量，通过制备除了粘结材料外还含有 a）氧化物以至少50重量％的量还原这样的氧化物，其仅形成成形或仅两性或仅有酸形成元素，彼此形成化合物或熔点高于1600℃的共晶体，和（ b）碳质还原剂和/或碳化物的量使得碳的量比将颗粒的氧化物转化为碳化物所需的量高1.05至1.35倍，或减少所需的量的0.66至0.02倍 颗粒的氧化物与金属元素组合，并且从含有过量碳和/或块状碳化物的颗粒和（β）从含碳缺陷的颗粒或由形成碱或两性的块状氧化物组装电荷（α） 或来自块状碳载体的（γ）和任选的来自铁添加剂的（δ），在不存在三氧化硼的情况下。

公开(公告)号：US08093537B2

公开(公告)日：2012-01-10

申请号：US12429473

申请日：2009-04-24

申请人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

发明人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

IPC分类号： H05B6/78 ,  A23L3/00

CPC分类号： H05B6/782 ,  A23L7/196 ,  A23L7/1975 ,  B65D2581/3422 ,  Y02A40/924 ,  Y02P60/833

摘要： A process for the production of short cooking time rice is characterized by that hulled rice of at least 10% moisture content, if required in packaging suitable for ready cooking, is heat treated for 1 to 30 minutes continuously or interrupted by equal or alternating capacity microwave radiation, to reach maximum 130° C. An apparatus for the production of short cooking time rice has a microwave furnace with a tunnel made from a suitable material, wherein the rice packed into packages is movable within the tunnel by a conveyor. Regarding the easy and short process, a remarkable energy saving is possible.

摘要翻译： 用于生产短烹饪时间米的方法的特征在于，如果在适合于准备烹饪的包装中需要，至少含有10％水分含量的水稻被连续热处理1至30分钟或通过相等或交替容量的微波中断 辐射，达到最高130℃。一种用于生产短烹饪时间米的设备具有由合适材料制成的隧道的微波炉，其中包装的米饭通过输送机在隧道内可移动。 关于简单和简短的过程，可以显着节能。

公开(公告)号：US20090206072A1

公开(公告)日：2009-08-20

申请号：US12429473

申请日：2009-04-24

申请人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

发明人： Horst Linn ,  Andras Vass ,  Ivanne Pallai ,  Gyula Fazekas ,  Janos Kovacs ,  Istvan Edes

IPC分类号： H05B6/78

CPC分类号： H05B6/782 ,  A23L7/196 ,  A23L7/1975 ,  B65D2581/3422 ,  Y02A40/924 ,  Y02P60/833

摘要： A process for the production of short cooking time rice is characterized by that hulled rice of at least 10% moisture content, if required in packaging suitable for ready cooking, is heat treated for 1 to 30 minutes continuously or interrupted by equal or alternating capacity microwave radiation, to reach maximum 130° C. An apparatus for the production of short cooking time rice comprises a microwave furnace with a tunnel made from a suitable material, wherein the rice packed into packages is movable within the tunnel by a conveyor. Regarding the easy and short process, a remarkable energy safing is possible.

摘要翻译： 用于生产短烹饪时间米的方法的特征在于，如果在适合于准备烹饪的包装中需要，至少含有10％水分含量的水稻被连续热处理1至30分钟或通过相等或交替容量的微波中断 辐射，达到最高130℃。一种用于生产短烹饪时间饭的设备包括具有由合适材料制成的隧道的微波炉，其中包装的米饭通过输送机在隧道内可移动。 关于简单和简短的过程，可以进行显着的能量保护。

公开(公告)号：US5793239A

公开(公告)日：1998-08-11

申请号：US920692

申请日：1997-08-29

申请人： Janos Kovacs ,  Kevin McCall

发明人： Janos Kovacs ,  Kevin McCall

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  Y10T307/858

摘要： A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

摘要翻译： 在另一电路内使用的复合负载电路包括至少一个放大晶体管。 复合负载电路包括并联连接的第一和第二晶体管。 每个负载晶体管具有接收公共控制电压的栅极。 每个负载晶体管也具有不同的导通阈值电压。 与负载晶体管并联连接的电阻限制了负载晶体管的有效阻抗。

公开(公告)号：US07232951B1

公开(公告)日：2007-06-19

申请号：US11299532

申请日：2005-12-12

申请人： Janos Kovacs

发明人： Janos Kovacs

IPC分类号： H01H9/02

CPC分类号： H02G3/081

摘要： Disclosed herein is a junction box having a housing and a plurality of straps. The housing includes a plurality of ribs with posts extending therefrom. Each one of the straps has a plurality of receiving areas defined by a contiguous radial surface, such as a countersink surface. The posts extend through the receiving areas and securingly retain the straps against the housing. In an exemplary embodiment of the present invention, the posts are substantially frustoconical prior to assembly and may be characterized as deformed frustrums after assembly.

摘要翻译： 本文公开了具有壳体和多个带子的接线盒。 壳体包括多个肋，肋具有从其延伸的柱。 每个带子具有由邻接的径向表面（例如埋头孔表面）限定的多个接收区域。 支柱延伸通过接收区域并将带固定地保持在壳体上。 在本发明的示例性实施例中，柱在组装之前基本上为截头圆锥形，并且可以在组装之后被表征为变形的楔形。

公开(公告)号：US6067655A

公开(公告)日：2000-05-23

申请号：US919868

申请日：1997-08-28

申请人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

发明人： Janos Kovacs ,  Ronald Kroesen ,  Jason Byrne

IPC分类号： H04R3/02 ,  H03M13/00

CPC分类号： H04R3/02

摘要： A burst error limiting symbol detector system includes a symbol detector circuit responsive to a truncated sample signal for detecting binary symbols encoded in a truncated sample signal with reference to at least one preselected reference level; a feedback equalizer circuit for providing a feedback equalizer signal for cancelling undesired samples in an input signal; a summing circuit, responsive to the input signal and the feedback equalizer signal for providing the truncated sample signal to the symbol detector circuit; and a feedback suppressor circuit responsive to the truncated sample being within a predetermined range of the preselected reference level for suppressing the feedback equalizer signal to prevent marginal detected binary symbols from contributing to the cancellation of undesired samples in the input signal.

摘要翻译： 突发错误限制符号检测器系统包括符号检测器电路，其响应于截取的采样信号，用于参考至少一个预选参考电平来检测以截断的采样信号编码的二进制符号; 反馈均衡器电路，用于提供用于消除输入信号中的不需要的采样的反馈均衡器信号; 响应于输入信号和反馈均衡器信号的加法电路，用于将截断的采样信号提供给符号检测器电路; 以及反馈抑制器电路，其响应于所述截断的样本在所述预选参考电平的预定范围内，以抑制所述反馈均衡器信号，以防止边缘检测到的二进制符号有助于消除所述输入信号中的不需要的采样。