Invention Grant
US06307229B2 Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips 失效
具有叠加位线和短路金属条的非易失性半导体存储器件结构

  • Patent Title: Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
  • Patent Title (中): 具有叠加位线和短路金属条的非易失性半导体存储器件结构
  • Application No.: US09081881
    Application Date: 1998-05-19
  • Publication No.: US06307229B2
    Publication Date: 2001-10-23
  • Inventor: Nicola ZatelliFederico PioBruno Vajana
  • Applicant: Nicola ZatelliFederico PioBruno Vajana
  • Priority: ITMI97A1167 19970520
  • Main IPC: H01L29788
  • IPC: H01L29788
Nonvolatile semiconductor memory device structure with superimposed bit lines and short-circuit metal strips
Abstract:
A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.
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