公开(公告)号：US06307229B2

公开(公告)日：2001-10-23

申请号：US09081881

申请日：1998-05-19

申请人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

发明人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

摘要翻译： 一种具有半导体材料层中的存储单元矩阵的非易失性半导体存储器件结构。 存储单元位于矩阵的行和列的交点处。 每个存储单元包括连接到行中的一个的控制栅电极，连接到一列的第一电极和第二电极。 这些行包括在第一方向上彼此平行延伸的多晶硅条，并且所述列由在与第一方向正交的第二方向上彼此平行延伸的金属条形成。 短路金属带被耦合以使存储器单元的第二电极短路。 列和短路带分别形成在第一金属层和第二金属层之间，第二金属层与第二金属层叠在一起，并被电介质层电绝缘。

公开(公告)号：US06255163B1

公开(公告)日：2001-07-03

申请号：US09330540

申请日：1999-06-11

申请人： Nicola Zatelli ,  Cesare Clementi ,  Carlo Cremonesi ,  Federico Pio

发明人： Nicola Zatelli ,  Cesare Clementi ,  Carlo Cremonesi ,  Federico Pio

IPC分类号： H01L21336

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11543

摘要： The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

摘要翻译： 通过在选择晶体管本身的源极和漏极区域处的N型注入来增加选择晶体管的驱动能力。 这种植入方便地在自对准蚀刻结束时制作，使用相同的自对准蚀刻掩模来定义存储元件的控制栅极区域和浮动栅极区域，保持电路区域被电路掩模覆盖。

公开(公告)号：US06180460B2

公开(公告)日：2001-01-30

申请号：US09337051

申请日：1999-06-21

申请人： Carlo Cremonesi ,  Federico Pio ,  Nicola Zatelli

发明人： Carlo Cremonesi ,  Federico Pio ,  Nicola Zatelli

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Process for manufacturing a non-volatile memory with memory cells arranged in rows and columns in a matrix structure, with source lines extending in parallel with and intercalated to said rows, the cells including MOS transistors having a floating gate and a control gate respectively formed in a first and a second polysilicon layers superimposed, the process including a first step of definition of regions of active area covered by a layer of thin oxide and delimited by regions of field oxide, a second step of deposition of the first polysilicon layer, a third step of etch of the first polysilicon layer through a first mask to separate the floating gates of cells belonging to a same row of the matrix, a fourth step of deposition of an intermediate dielectric layer and of the second polysilicon layer, a fifth step of definition of the rows through self-aligned selective etch of said second polysilicon layer, of the intermediate dielectric layer and of the first polysilicon layer, the self-aligned selective etch determining in the source lines excavations in correspondence of regions in which the first polysilicon layer has been removed during the third step, and a sixth step of dopant introduction in the regions of active area for the formation of regions of source and drain of the cells. Before the fourth step a selective introduction of dopant is provided in correspondence of regions of the common source lines in which the excavations will be formed, for the formation of doped regions deeper than the excavations.

摘要翻译： 用于制造具有以矩阵结构排列成行和列的存储单元的非易失性存储器的处理，其中源极线与所述行并联延伸并插入到所述行中，所述单元包括具有浮置栅极和控制栅极的MOS晶体管， 叠加第一和第二多晶硅层，该方法包括第一步骤，定义由氧化物薄膜覆盖并由场氧化物区域限定的有源区域的区域，第一多晶硅层沉积的第二步骤 通过第一掩模蚀刻第一多晶硅层以分离属于同一行矩阵的单元的浮动栅极的步骤，中间介电层和第二多晶硅层的沉积的第四步骤，第五步骤的定义 的行通过所述第二多晶硅层，中间介电层和第一多晶硅层的自对准选择性蚀刻，sel 在对应于在第三步骤期间去除了第一多晶硅层的区域的源极线挖掘中确定f-对准的选择性蚀刻以及在有源区域中的掺杂剂引入的第六步骤，用于形成源区域和 细胞排泄。 在第四步骤之前，对应于将形成挖掘的共同源极线的区域提供选择性引入掺杂剂，以形成比挖掘更深的掺杂区域。

公开(公告)号：US6151245A

公开(公告)日：2000-11-21

申请号：US215650

申请日：1998-12-17

申请人： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

发明人： Federico Pio ,  Nicola Zatelli ,  Laurent Sourgen ,  Mathieu Lisart

IPC分类号： G11C16/02 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC分类号： H01L27/115 ,  H01L27/02

摘要： An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

摘要翻译： EEPROM单元被描述为具有在第一金属层中优选形成的屏蔽金属结构，并且在浮动栅极端子处基本上覆盖关系。 这样可以通过测量浮栅端子上的电荷量来获得异常读数的可能性。 可以提供要在第三和随后的金属层中形成的另外的筛选金属结构，以完全覆盖电池并提供额外的防止异常读数的保护。

公开(公告)号：US06381173B1

公开(公告)日：2002-04-30

申请号：US09686362

申请日：2000-10-10

申请人： Nicola Zatelli

发明人： Nicola Zatelli

IPC分类号： G11C1600

CPC分类号： G11C16/0433 ,  G11C16/0416

摘要： A serial-flash, EPROM, EEPROM, or flash EEPROM nonvolatile memory in AMG configuration includes a byte enable transistor having an input terminal, connected to a control gate line and receives an input voltage, an output terminal, connected to at least one memory cell and supplying an output voltage, a control terminal connected to a word line, and a bulk region housing conductive regions connected to the input and output terminals. The byte enable transistor is a P-channel MOS transistor, the bulk region whereof is biased to a bulk voltage that is not lower than the input voltage.

摘要翻译： AMG配置中的串行闪存，EPROM，EEPROM或快闪EEPROM非易失性存储器包括一个字节使能晶体管，其具有连接到控制栅极线并接收输入电压的输入端子，连接到至少一个存储器单元的输出端子 并且提供输出电压，连接到字线的控制端子和容纳连接到输入和输出端子的导电区域的体区域。 字节使能晶体管是P沟道MOS晶体管，其体区被偏置为不低于输入电压的体电压。

公开(公告)号：US06313480B1

公开(公告)日：2001-11-06

申请号：US09209049

申请日：1998-12-09

申请人： Nicola Zatelli ,  Carlo Cremonesi

发明人： Nicola Zatelli ,  Carlo Cremonesi

IPC分类号： H01L2358

CPC分类号： H01L22/34

摘要： The structure allows checking an integrated electronic device comprising an oxide layer to be measured located above a doped pocket of a wafer of doped semiconductor material and arranged adjacent to a gate region of polycrystalline semiconductor material. The structure is formed at a suitable point of the wafer and comprises an oxide test region of the same material, having the same thickness and the same electrical characteristics as the oxide layer to be measured and a polycrystalline region of the same material, having the same thickness and the same electrical characteristics as the gate region. The polycrystalline region extends preferably along the perimeter of a square and delimits laterally the oxide test region, the area of which is greater than the area of the oxide layer to be measured so as to allow non-destructive testing, on-line, of the oxide layer to be measured during an early stage of the manufacturing process.

摘要翻译： 该结构允许检查集成的电子器件，其包括位于掺杂半导体材料的晶片的掺杂口袋上方并且邻近多晶半导体材料的栅极区域布置的待测量的氧化物层。 该结构形成在晶片的合适点处，并且包括具有与待测量的氧化物层相同的厚度和相同电特性的相同材料的氧化物测试区域和具有相同材料的相同材料的多晶区域 厚度和与栅极区域相同的电特性。 多晶区域优选地沿着正方形的周边延伸并且横向限定氧化物测试区域，该区域的面积大于待测量的氧化物层的面积，以允许在线地进行非破坏性测试 在制造过程的早期阶段要测量的氧化物层。

公开(公告)号：US06319780B2

公开(公告)日：2001-11-20

申请号：US09727266

申请日：2000-11-29

申请人： Barbara Crivelli ,  Daniela Peschiaroli ,  Elisabetta Palumbo ,  Nicola Zatelli

发明人： Barbara Crivelli ,  Daniela Peschiaroli ,  Elisabetta Palumbo ,  Nicola Zatelli

IPC分类号： H01L218234

CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/11539 ,  Y10S438/981

摘要： Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.

摘要翻译： 有源区域和体区形成在用于形成低压MOS晶体管，高压MOS晶体管和EPROM单元的衬底中。 在基板上形成热氧化层，在热氧化层上形成第一多晶硅层。 选择性地去除多晶硅层以形成EPROM单元的浮置栅电极，并且还形成EPROM单元的源极和漏极区。 高电压MOS晶体管的有源区域被暴露，形成一层高温氧化物并氮化。 低电压MOS晶体管的有源区域被暴露，并且在暴露的区域上形成一层热氧化物。 沉积第二多晶硅层，然后选择性地去除以形成低压和高压MOS晶体管的栅电极以及EPROM单元的控制栅电极。

公开(公告)号：US06686241B2

公开(公告)日：2004-02-03

申请号：US09798778

申请日：2001-03-02

申请人： Massimo Ati ,  Alfonso Maurelli ,  Nicola Zatelli

发明人： Massimo Ati ,  Alfonso Maurelli ,  Nicola Zatelli

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.

摘要翻译： 该方法适用于具有排列成行和列的单元的非易失性半导体存储器，其中每个单元具有分别连接到行线的第一端子，第二端子和第三端子到列线，以及 通过相应的连接条连接到公共节点。 为了形成具有低电阻率的连接并因此节省半导体面积，该方法提供了形成覆盖第一端子和第三端子的连接条的氧化物层，沿着连接条形成通道直到 其表面被暴露，并且用具有比连接条的电阻率低的材料的材料填充通道。

公开(公告)号：US06624471B2

公开(公告)日：2003-09-23

申请号：US09960254

申请日：2001-09-20

申请人： Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

发明人： Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

IPC分类号： H01L2976

CPC分类号： H01L29/41725 ,  H01L29/7835

摘要： A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

摘要翻译： 一种具有漏极区域的横向DMOS晶体管，其包括漏电极接触的高浓度部分和由沟道区域限定的低浓度部分。 除了常规的源极，漏极，体和栅电极之外，晶体管还具有与漏极区域的靠近沟道的低浓度部分的点接触的附加电极。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可以用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

公开(公告)号：US06576950B1

公开(公告)日：2003-06-10

申请号：US09684156

申请日：2000-10-06

申请人： Paolo Cappelletti ,  Alfonso Maurelli ,  Nicola Zatelli

发明人： Paolo Cappelletti ,  Alfonso Maurelli ,  Nicola Zatelli

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

摘要： The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

摘要翻译： 存储单元是具有单层多晶硅的类型，并且包括感测晶体管和选择晶体管。 感测晶体管包括形成在半导体材料的衬底的第一有源区中的具有第二类型导电性的控制栅极区域和相对于第一有源区域横向延伸的浮动栅极区域。 感测晶体管的控制栅极区域被具有第一类型导电性的第一阱围绕，并且又由具有第二类导电性的第二阱围绕，下面和侧面，从而形成三阱结构。 可以在与第一有源区相邻的第二有源区中形成第二三阱结构，并且可以适应感测晶体管和选择晶体管的导电区。