A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.