公开(公告)号：US08817434B2

公开(公告)日：2014-08-26

申请号：US13270298

申请日：2011-10-11

Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/00

CPC classification number: H02H9/00 ,  H01L27/0266

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract translation: 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。

公开(公告)号：US20130208379A1

公开(公告)日：2013-08-15

申请号：US13369455

申请日：2012-02-09

Applicant: Chang-Tzu WANG ,  Tien-Hao TANG ,  Kuan-Cheng SU

Inventor： Chang-Tzu WANG ,  Tien-Hao TANG ,  Kuan-Cheng SU

IPC: H02H9/04

CPC classification number: H01L27/0262 ,  H01L29/7436 ,  H01L29/87

Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

Abstract translation: 半导体ESD保护装置包括基板; 第一掺杂阱，其设置在所述衬底中并且具有第一导电性; 具有第一导电性的第一掺杂区域设置在第一掺杂阱中; 第二掺杂区域，具有设置在第一掺杂阱中的第二导电体; 以及设置在所述衬底中的外延层，其中所述外延层具有具有第一导电性的第三掺杂区域和具有第二导电性的第四掺杂区域彼此分离。 由此在第一掺杂区，第一掺杂阱和第三掺杂区之间形成第一双极结型晶体管（BJT）等效电路; 在第二掺杂区，第一掺杂阱和第四掺杂区之间形成第二BJT等效电路; 并且第一BJT等效电路和第二BJT等效电路具有不同的多数载波。

公开(公告)号：US08510635B2

公开(公告)日：2013-08-13

申请号：US12979914

申请日：2010-12-28

Applicant: Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

Inventor： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC: G11C29/00

CPC classification number: G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract translation: 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

公开(公告)号：US08467162B2

公开(公告)日：2013-06-18

申请号：US12981521

申请日：2010-12-30

Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H3/20 ,  H02H9/04

CPC classification number: H02H3/20 ,  H01L27/0262 ,  H01L2924/1301 ,  H01L2924/1304 ,  H02H9/04 ,  H02H9/046

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

公开(公告)号：US20110193586A1

公开(公告)日：2011-08-11

申请号：US12703949

申请日：2010-02-11

Applicant: Sung-Nien Kuo ,  Yuan-Yu Hsieh ,  Wen-Hsiung Ko ,  Jih-San Lee ,  Kuei-Chi Juan ,  Kuan-Cheng Su

Inventor： Sung-Nien Kuo ,  Yuan-Yu Hsieh ,  Wen-Hsiung Ko ,  Jih-San Lee ,  Kuei-Chi Juan ,  Kuan-Cheng Su

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2621 ,  G01R31/2642 ,  G01R31/2849 ,  H01L22/34

Abstract: An AC stress test circuit for HCI degradation evaluation in semiconductor devices includes a ring oscillator circuit, first and second pads, and first and second isolating switches. The ring oscillator circuit has a plurality of stages connected in series to form a loop. Each of the stages comprises a first node and a second node. The first and second isolating switches respectively connect the first and second pads to the first and second nodes of a designated stage and both are switched-off during ring oscillator stressing of the designated stage. The present invention also provides a method of evaluating AC stress induced HCI degradation, and a test structure.

Abstract translation: 用于半导体器件中的HCI劣化评估的AC应力测试电路包括环形振荡器电路，第一和第二焊盘以及第一和第二隔离开关。 环形振荡器电路具有多个串联连接以形成环路。 每个级包括第一节点和第二节点。 第一和第二隔离开关分别将第一和第二焊盘连接到指定级的第一和第二节点，并且在指定阶段的环形振荡器应力期间两者都被切断。 本发明还提供了一种评估AC应力诱导的HCI降解的方法和测试结构。

公开(公告)号：US5691234A

公开(公告)日：1997-11-25

申请号：US511065

申请日：1995-08-03

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/02 ,  H01L21/28

CPC classification number: H01L27/0255

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US08963202B2

公开(公告)日：2015-02-24

申请号：US13369455

申请日：2012-02-09

Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436 ,  H01L29/87

Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

Abstract translation: 半导体ESD保护装置包括基板; 第一掺杂阱，其设置在所述衬底中并且具有第一导电性; 具有第一导电性的第一掺杂区域设置在第一掺杂阱中; 第二掺杂区域，具有设置在第一掺杂阱中的第二导电体; 以及设置在所述衬底中的外延层，其中所述外延层具有具有所述第一导电性的第三掺杂区域和具有第二导电性的第四掺杂区域彼此分离。 由此在第一掺杂区，第一掺杂阱和第三掺杂区之间形成第一双极结型晶体管（BJT）等效电路; 在第二掺杂区，第一掺杂阱和第四掺杂区之间形成第二BJT等效电路; 并且第一BJT等效电路和第二BJT等效电路具有不同的多数载波。

公开(公告)号：US20090027074A1

公开(公告)日：2009-01-29

申请号：US11829104

申请日：2007-07-27

Applicant: Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

Inventor： Wen-Hsiung Ko ,  Wen-Chun Chang ,  Kuan-Cheng Su

IPC: G01R31/02 ,  H01L21/66 ,  H01L23/58

CPC classification number: G01R31/2875 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a wafer level test structure and a test method; in which, a heating plate is formed on the wafer for heating a structure to be tested positioned above or adjacent to the heating plate. The heating plate produces heat by electrically connecting to a current. Thus, the heat provided by the heating plate and the electric input/output into/from the structure to be tested are controlled separately and not influenced each other.

Abstract translation: 本发明公开了一种晶圆级测试结构和测试方法; 其中，在晶片上形成加热板，用于加热待加热板上方或附近的待测试结构。 加热板通过电连接到电流产生热量。 因此，加热板提供的热量和进入/待测结构的电输入/输出分开控制，彼此不相互影响。

公开(公告)号：US06500389B1

公开(公告)日：2002-12-31

申请号：US09561117

申请日：2000-04-28

Applicant: Hsiao-Pang Chou ,  Kuan-Cheng Su

Inventor： Hsiao-Pang Chou ,  Kuan-Cheng Su

IPC: G01N3096

CPC classification number: H01J37/32211 ,  H01J37/32935

Abstract: A plasma arcing sensor is used to increase the frequency of plasma arcing by way of neutralization of positive charges and negative charges. When the plasma arcing can be predicted, the process parameters to prevent from the plasma arcing can be carried out. The plasma arcing sensor comprises a top conductive layer formed over a substrate. A conductive layer is disposed between the top conductive layer and the wafer where the conductive layer and the top conductive layer are electrically isolated with dielectrics.

Abstract translation: 等离子体电弧传感器用于通过中和正电荷和负电荷来增加等离子体电弧的频率。 当可以预测等离子体电弧时，可以进行防止等离子体电弧放电的工艺参数。 等离子体电弧传感器包括在衬底上形成的顶部导电层。 导电层设置在导电层和晶片之间，其中导电层和顶部导电层与电介质电隔离。

公开(公告)号：US5918127A

公开(公告)日：1999-06-29

申请号：US650350

申请日：1996-05-20

Applicant: Chen-Wei Lee ,  Kuan-Cheng Su

Inventor： Chen-Wei Lee ,  Kuan-Cheng Su

IPC: H01L21/8246 ,  H01L27/02 ,  H01L27/112

CPC classification number: H01L27/0266 ,  H01L27/112

Abstract: A semiconductor fabrication method that enhances the ESD (electrostatic discharge) protection capability of an ESD protective device provided in an integrated circuit such as a mask-programmed ROM, allows the mask-programmed ROM to be downsized while still providing adequate ESD protection capability, and allows the mask-programmed ROM to be fabricated in a smaller size, while nonetheless providing adequate ESD protection capability for the internal circuit. Initially, a mask for the ion implantation process for the ROM is prepared. The mask is patterned additionally with a plurality of strips used to define breakdown voltage controlling areas in the ESD protective device. Then, the ion implantation process is performed through the mask so as to form the breakdown voltage controlling areas each beneath the drain of the n-type CMOS transistor. The breakdown voltage controlling areas are heavily doped, thereby reducing the breakdown voltage at the junction between the drain and the p-well in the n-type CMOS transistor. This enhances the ESD protection capability of the integrated circuit.

Abstract translation: 提高ESD掩模编程的集成电路中提供的ESD保护装置的ESD（静电放电）保护能力的半导体制造方法允许掩模编程的ROM小型化，同时仍然提供足够的ESD保护能力， 允许以较小的尺寸制造掩模编程的ROM，同时为内部电路提供足够的ESD保护能力。 首先，制备用于ROM的离子注入工艺的掩模。 该掩模附加地具有用于限定ESD保护装置中的击穿电压控制区域的多个条带。 然后，通过掩模进行离子注入工艺，以便在n型CMOS晶体管的漏极下形成击穿电压控制区。 击穿电压控制区域被重掺杂，从而降低n型CMOS晶体管中的漏极和p阱之间的结点处的击穿电压。 这增强了集成电路的ESD保护能力。