公开(公告)号：US06383883B1

公开(公告)日：2002-05-07

申请号：US09173831

申请日：1998-10-16

Applicant: Yao-Chin Cheng ,  Kuan-Cheng Su

Inventor： Yao-Chin Cheng ,  Kuan-Cheng Su

IPC: H01L2100

CPC classification number: H01L29/6659 ,  H01L29/7833

Abstract: A method of reducing junction capacitance of a source/drain region. A gate oxide layer is formed on a first conductive type substrate. A polysilicon layer is formed and patterned on the gate. Light second conductive type ions are implanted into the substrate with the polysilicon layer as a mask. An insulation layer is formed to cover a side wall of the polysilicon layer. A first step heavy of ion implantation with second conductive type ions is perform to the substrate using the polysilicon layer and the spacer as mask, so that a heavily doped region is formed. A second step of heavy ion implantation with the second conductive type ions is performed to the substrate using the polysilicon layer and the spacer as masks, so that the heavily doped region is broadened and deepened with a smooth ion distribution profile.

Abstract translation: 一种减少源/漏区的结电容的方法。 栅极氧化层形成在第一导电类型的衬底上。 在栅极上形成并图案化多晶硅层。 将光第二导电型离子注入到具有多晶硅层作为掩模的衬底中。 形成绝缘层以覆盖多晶硅层的侧壁。 利用第二导电型离子进行离子注入的第一步是使用多晶硅层和间隔物作为掩模进行衬底，从而形成重掺杂区域。 使用多晶硅层和间隔物作为掩模，对基板进行与第二导电型离子的重离子注入的第二步骤，使得重掺杂区域以平滑的离子分布分布变宽和加深。

公开(公告)号：US08648421B2

公开(公告)日：2014-02-11

申请号：US13290399

申请日：2011-11-07

Applicant: Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L23/60

CPC classification number: H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

Abstract translation: 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

公开(公告)号：US20120166130A1

公开(公告)日：2012-06-28

申请号：US12979914

申请日：2010-12-28

Applicant: Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

Inventor： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC: G06F19/00

CPC classification number: G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract translation: 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

公开(公告)号：US07589551B1

公开(公告)日：2009-09-15

申请号：US12107772

申请日：2008-04-23

Applicant: Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

Inventor： Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2858 ,  G01R31/2884

Abstract: To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated in the test region coupled to an output of the oscillator module, and a select transistor fabricated in the test region having a gate terminal coupled to an output of the diode module, a second terminal coupled to a gate of the test device, and a third terminal coupled to a test voltage source.

Abstract translation: 为了在晶片中更容易进行交流（AC）应力测试，用于对在晶片的测试区域中制造的测试装置进行AC应力测试的AC应力测试电路包括在测试区域中制造的振荡器模块， 制造在耦合到振荡器模块的输出的测试区域中的二极管模块，以及制造在测试区域中的选择晶体管，其具有耦合到二极管模块的输出的栅极端子，耦合到测试装置的栅极的第二端子 以及耦合到测试电压源的第三端子。

公开(公告)号：US06171899B2

公开(公告)日：2001-01-09

申请号：US09267535

申请日：1999-03-12

Applicant: Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

Inventor： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76838

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.

Abstract translation: 一种制造电容器的方法。 在所提供的基板上形成第一金属层。 在第一金属层上形成电介质膜。 电介质膜可以是单层结构或包括各种介电材料的多层结构。 进行快速热处理（RTP），例如快速热退火或等离子体处理，以提高电介质膜的质量。 进行光刻和蚀刻处理以去除电介质膜和第一金属层的一部分以暴露层间电介质层的一部分。 剩余的第一导电层用作下电极。 在暴露的层间电介质层和电介质膜上进行常规的互连工艺。 例如，在暴露的层间电介质层和电介质膜上形成胶层。 第二金属层形成在胶层上。 执行光刻和蚀刻工艺以去除第二导电层的一部分。 残留在层间电介质层上的第二金属层用作互连布线。 残留在电介质膜上的胶层用作上电极。

公开(公告)号：US5665995A

公开(公告)日：1997-09-09

申请号：US429603

申请日：1995-04-27

Applicant: Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract translation: 具有单元阵列的ROM器件具有形成在衬底中的导体。 形成绝缘体，平行导体与线区域正交形成，薄至约2000安。 在导体上形成厚度约为3000或更小的玻璃绝缘体被回流。 形成玻璃绝缘体上的触点和金属层。 抗蚀剂被图案化并用于蚀刻金属中的抗蚀剂图案。 在还原气体气氛中，通过在小于或等于约520℃退火器件使杂质离子激活之前，用厚度约为1000的层去除第二抗蚀剂和器件钝化。 抗蚀剂除去后，形成第二抗蚀剂并用定制的编码图案曝光以形成掩模。 离子以约1E14和3E14原子/ cm2的剂量注入到基底中，其能量小于或等于200keV，通过绝缘体中的开口与导体相邻。

公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/112 ,  H01L29/42368 ,  Y10S438/981

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract translation: 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US5504030A

公开(公告)日：1996-04-02

申请号：US505050

申请日：1995-07-21

Applicant: Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

Inventor： Chen-Hui Chung ,  Kuan-Cheng Su ,  Yi-Chung Sheng

IPC: H01L21/8246

CPC classification number: H01L27/11246 ,  Y10S438/981

Abstract: A method of fabricating memory cells of a mask ROM device. A plurality of source/drain regions extending along a first direction is formed by implanting impurities into a semiconductor substrate, constituting bit lines of the memory cells. A code oxide layer is formed on a designated area of the semiconductor substrate defined by a barrier layer using a liquid-phase deposition process, whereby a multi-state mask ROM is fabricated by repeatedly performing the liquid-phase deposition process to form a series of coding oxide layers having increasing thicknesses. A gate oxide layer is formed on a portion of the semiconductor substrate not covered by the coding oxide layers. The thickness of the gate oxide layer is smaller than that of the coding oxide layers. A plurality of gate electrodes extending along a second direction orthogonal to the first direction is formed by depositing and patterning a conducting layer on the coding oxide layer and the gate oxide layer, constituting word lines of said memory cells. The cross area of every two adjacent bit lines and one word line thereby forms a memory cell of the mask ROM wherein threshold voltages of the memory cells are altered proportional to the thicknesses of the gate oxide layer and the coding oxide layers.

Abstract translation: 一种制造掩模ROM器件的存储单元的方法。 沿着第一方向延伸的多个源极/漏极区域通过将杂质注入构成存储器单元的位线的半导体衬底中而形成。 在通过液相沉积工艺由阻挡层限定的半导体衬底的指定区域上形成编码氧化物层，由此通过反复进行液相沉积工艺以形成一系列 编码具有增加的厚度的氧化物层。 在不被编码氧化物层覆盖的半导体衬底的一部分上形成栅氧化层。 栅极氧化物层的厚度小于编码氧化物层的厚度。 通过在构成所述存储单元的字线的编码氧化物层和栅极氧化物层上沉积和图案化导电层来形成沿着与第一方向正交的第二方向延伸的多个栅电极。 因此，每两个相邻位线和一个字线的横截面形成掩模ROM的存储单元，其中存储单元的阈值电压与栅极氧化物层和编码氧化物层的厚度成比例地变化。

公开(公告)号：US08817434B2

公开(公告)日：2014-08-26

申请号：US13270298

申请日：2011-10-11

Applicant: Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H02H9/00

CPC classification number: H02H9/00 ,  H01L27/0266

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract translation: 示例性ESD保护装置适用于高耐压I / O电路，并且包括堆叠晶体管和栅极接地晶体管，例如非轻掺杂漏极型栅极接地晶体管。 堆叠晶体管和栅极接地晶体管在I / O焊盘和高耐压I / O电路的接地电压之间并联电耦合。

公开(公告)号：US08510635B2

公开(公告)日：2013-08-13

申请号：US12979914

申请日：2010-12-28

Applicant: Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

Inventor： Yun-Chi Yang ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC: G11C29/00

CPC classification number: G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract translation: 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。