发明授权
US06423558B1 Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures
失效
具有多层互连结构的集成电路(IC)芯片的制造方法
- 专利标题: Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures
- 专利标题(中): 具有多层互连结构的集成电路(IC)芯片的制造方法
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申请号: US09512780申请日: 2000-02-25
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公开(公告)号: US06423558B1公开(公告)日: 2002-07-23
- 发明人: Yasuhiro Maeda , Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
- 申请人: Yasuhiro Maeda , Masahiro Ishida , Takahiro Yamaguchi , Mani Soma
- 主分类号: G01R3126
- IPC分类号: G01R3126
摘要:
In a method for fabricating an LSI in which primitive devices such as transistors are formed on a semiconductor substrate and a plurality of interconnect layers are formed thereover to provide sub-circuits of successively larger scale and increasing complexity including sub-circuits which are formed by a connection of the primitive devices and sub-circuits of a larger scale which are formed by a connection of the sub-circuits, under a condition that an intermediate interconnect layer is formed, an exhaustive test, a functional test, a stuck-at fault test, a quiescent power supply current test or the like takes place with respect to the primitive devices or the sub-circuits which are wired together by the intermediate interconnect layer, and subsequently, a wiring connection test takes place after the formation of each subsequent interconnect layer. A fault coverage is improved while a testing cost and a fabricating cost are reduced.
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