A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.