公开(公告)号：US06452857B1

公开(公告)日：2002-09-17

申请号：US09563186

申请日：2000-05-02

申请人： Thomas Alofs ,  Nicolas Grossier

发明人： Thomas Alofs ,  Nicolas Grossier

IPC分类号： G11C800

CPC分类号： G11C8/18

摘要： A circuit for controlling the storage of data in a memory element including a bistable device having a first input for receiving an address input and a second input for receiving a clock signal and circuitry for receiving the output of the bistable device and the clock signal and providing a write enable signal for the memory, the circuitry being arranged so that the write enable signal is enabled in response to a first transition in the clock signal from a first state to a second state and disabled in response to the clock signal making the next transition back to the first state, the first and next transitions being in the same clock cycle.

摘要翻译： 一种用于控制存储元件中存储数据的电路，包括具有用于接收地址输入的第一输入端的双稳态器件和用于接收时钟信号的第二输入端和用于接收双稳态器件输出和时钟信号的电路， 用于存储器的写使能信号，所述电路被布置成使得所述写使能信号响应于所述时钟信号中的第一转变从第一状态到第二状态而被使能，并且响应于所述时钟信号进行下一转换而被禁止 回到第一状态，第一个和下一个转换处于相同的时钟周期。

公开(公告)号：US20120240128A1

公开(公告)日：2012-09-20

申请号：US13497342

申请日：2009-09-30

申请人： Thomas Alofs ,  Nicolas Lafargue

发明人： Thomas Alofs ,  Nicolas Lafargue

IPC分类号： G06F9/46

CPC分类号： G06F11/348 ,  G06F11/349

摘要： There is disclosed a solution for obtaining Memory Access Performance metrics in an electronic system comprising a Data Processing Unit, DPU and a synchronous memory device external to the DPU and coupled to the DPU through a memory bus. There is used mixed software and hardware dedicated resources, wherein at least a hardware part of the dedicated resources is comprised in the memory device.

摘要翻译： 公开了一种用于在包括数据处理单元，DPU和DPU外部的同步存储器设备的电子系统中获得存储器访问性能度量的解决方案，并且通过存储器总线耦合到DPU。 使用混合的软件和硬件专用资源，其中专用资源的至少硬件部分包括在存储器装置中。

公开(公告)号：US07404069B2

公开(公告)日：2008-07-22

申请号：US11368332

申请日：2006-03-03

申请人： Thomas Alofs

发明人： Thomas Alofs

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F9/3806

摘要： A device generates an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type. The device includes: a first block to receive a first signal representative of an actually executed instruction; a second block to receive a second signal representative of an expanded instruction; a third block to receive a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by the microcontroller, microprocessor or data processing unit; at least one register to store consecutive addresses pointed to by a program counter; a fourth block to process the first, second and third signals in order to determine a pair having a source address and a destination address for an address branch, when appropriate; and a storage unit to store said address pair.

摘要翻译： 设备为微控制器单元，微处理器或具有包括至少一个预测指令和扩展类型的至少一个指令的指令集的数据处理单元生成地址分支迹线。 该装置包括：第一块，用于接收表示实际执行的指令的第一信号; 接收表示扩展指令的第二信号的第二块; 第三块，用于接收代表由微控制器，微处理器或数据处理单元执行的程序的源地址和目的地地址之间的不连续分支的第三信号; 至少一个用于存储由程序计数器指向的连续地址的寄存器; 第四块，用于处理第一，第二和第三信号，以便在适当时确定具有地址分支的源地址和目的地地址的对; 以及存储单元，用于存储所述地址对。

公开(公告)号：US20050251661A1

公开(公告)日：2005-11-10

申请号：US11031956

申请日：2005-01-07

申请人： Laurent Uguen ,  Sebastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

发明人： Laurent Uguen ,  Sebastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

IPC分类号： G06F9/00 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3838

摘要： A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

摘要翻译： 传送保护值的方法和诸如用于数字信号处理的处理器的计算机系统，包括利用该方法的一组并行执行单元。 与其中一个执行单元相关联地保存有一组主要的保护指示符。 如果其他执行单元需要特定保护指示灯的保护值，则将发送保护指令给持有主保护值的执行单元。 sendguard指令被保存在与该执行单元的主要指令的单独队列中。 在执行单元中提供电路，以避免即使在前面的保护修改指令的上下文中发送发送指令的停止。

公开(公告)号：US07661040B2

公开(公告)日：2010-02-09

申请号：US10075113

申请日：2002-02-13

申请人： Marc Beaujoin ,  Thomas Alofs ,  Paul Armagnat

发明人： Marc Beaujoin ,  Thomas Alofs ,  Paul Armagnat

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/003 ,  G11C29/38

摘要： The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

摘要翻译： 顺序访问存储器阵列能够存储每个n位的p个字。 每个由n个测试位组成的这些p个测试字被写入存储器阵列中，p个测试字被顺序提取，并且对于每个当前提取的单词，组成它们的n个测试位被顺序地与n个相应的预期数据位进行比较 提取下一个测试字。

公开(公告)号：US07496737B2

公开(公告)日：2009-02-24

申请号：US11031956

申请日：2005-01-07

申请人： Laurent Uguen ,  Sébastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

发明人： Laurent Uguen ,  Sébastien Ferroussat ,  Andrew Cofler ,  Thomas Alofs

IPC分类号： G06F9/00

CPC分类号： G06F9/3885 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3838

摘要： A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

摘要翻译： 传送保护值的方法和诸如用于数字信号处理的处理器的计算机系统，包括利用该方法的一组并行执行单元。 与其中一个执行单元相关联地保存有一组主要的保护指示符。 如果其他执行单元需要特定保护指示灯的保护值，则将发送保护指令给持有主保护值的执行单元。 sendguard指令被保存在与该执行单元的主要指令的单独队列中。 在执行单元中提供电路，以避免即使在前面的保护修改指令的上下文中发送发送指令的停止。

公开(公告)号：US20060224868A1

公开(公告)日：2006-10-05

申请号：US11368332

申请日：2006-03-03

申请人： Thomas Alofs

发明人： Thomas Alofs

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F9/3806

摘要： A device for generating an address branch trace for a microcontroller unit, a microprocessor or a data processing unit having a set of instructions including at least one predicated instruction and at least one instruction of the expanded type, said device including: means for receiving a first signal representative of an actually executed instruction; means for receiving a second signal representative of an expanded instruction; means for receiving a third signal representative of a discontinuity branch between a source address and a destination address of a program executed by said microcontroller, microprocessor or data processing unit; means for storing consecutive addresses pointed by a program counter; means for processing said first, second and third signals in order to determine a pair comprised of a source address and a destination address for an address branch, when appropriate; and means for storing said address pair.

摘要翻译： 一种用于产生用于微控制器单元的地址分支迹线的装置，微处理器或具有包括至少一个预定指令和至少一个扩展类型的指令的指令集的数据处理单元，所述装置包括：用于接收第一 表示实际执行的指令的信号; 用于接收表示扩展指令的第二信号的装置; 用于接收表示由所述微控制器，微处理器或数据处理单元执行的程序的源地址和目的地地址之间的不连续分支的第三信号的装置; 用于存储由程序计数器指向的连续地址的装置; 用于处理所述第一，第二和第三信号的装置，以便在适当时确定包括地址分支的源地址和目的地地址的对; 以及用于存储所述地址对的装置。

公开(公告)号：US06593777B2

公开(公告)日：2003-07-15

申请号：US10141621

申请日：2002-05-08

申请人： Thomas Alofs

发明人： Thomas Alofs

IPC分类号： H03K19082

CPC分类号： H03K17/005 ,  H03K3/037

摘要： A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.