Invention Grant
- Patent Title: Process for forming a multi-level thin-film electronic packaging structure
- Patent Title (中): 用于形成多层薄膜电子封装结构的方法
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Application No.: US09886326Application Date: 2001-06-21
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Publication No.: US06678949B2Publication Date: 2004-01-20
- Inventor: Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
- Applicant: Chandrika Prasad , Roy Yu , Richard L. Canull , Giulio DiGiacomo , Ajay P. Giri , Lewis S. Goldmann , Kimberley A. Kelly , Bouwe W. Leenstra , Voya R. Markovich , Eric D. Perfecto , Sampath Purushothaman , Joseph M. Sullivan
- Main IPC: H05K334
- IPC: H05K334

Abstract:
A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.
Public/Granted literature
- US20010037565A1 Process for forming a multi-level thin-film electronic packaging structure Public/Granted day:2001-11-08
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